Sr. ASIC Design Verification Engineer [Starshield]

Anysilicon; Irvine, Northern (CA, KY); Híbrido; USD 140 000 - 200 000; Tempo integral

Resumo da oferta

SpaceX is seeking a Sr. ASIC Design Verification Engineer for its Starshield team, focusing on advanced FPGA/ASIC verification for space and ground infrastructure.

You will lead verification at block and system levels and develop test harnesses and UVM-based testbenches. The role requires 5+ years in design verification, strong SystemVerilog and Python skills, and experience with constrained random verification.

Qualificações

• Bachelor's degree in electrical/computer engineering or computer science.
• 5+ years of design verification and test bench development experience.

Responsabilidades

• Conduct digital ASIC verification at block and system levels.
• Lead verification test plans and milestones.
• Develop test harnesses and sequences for testing designs.
• Create SystemVerilog testbench infrastructure (UVM and non-UVM).
• Execute test plans, run regressions, and ensure code and functional coverage closure.
• Automate test case generation using Python and MATLAB.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.

Conhecimentos

UVM/OVM/VMM

SystemVerilog

Python scripting

MATLAB

Constrained random

RTL verification

Formação académica

Bachelor's degree in electrical/computer engineering or computer science

Descrição da oferta de emprego

SpaceX is seeking a Sr. ASIC Design Verification Engineer for its Starshield team, which utilizes Starlink technology to support national security initiatives. The role focuses on developing advanced FPGAs and ASICs for space and ground infrastructures, contributing to the goal of enabling human life on Mars.

Responsibilities:

• Conduct digital ASIC verification at both block and system levels.
• Lead and execute verification test plans, including development and milestones.
• Develop test harnesses and sequences for testing designs, particularly DSP blocks.
• Create SystemVerilog testbench infrastructure (UVM and non-UVM).
• Execute test plans, run regressions, and ensure code and functional coverage closure.
• Automate test case generation using Python and MATLAB.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
• Act as a hands-on self-starter to fully verify complex digital designs.

Qualifications:

• Bachelor's degree in electrical engineering, computer engineering, or computer science.
• 5+ years of experience in design verification and test bench development.

Skills:

• Advanced degree in electrical engineering or computer engineering (preferred).
• Experience with verification methodologies such as UVM/OVM/VMM.
• Strong object-oriented programming skills.
• Proficient problem-solving and coding abilities.
• Experience in constrained random verification.
• Expertise in developing test plans and analyzing results.
• Familiarity with scripting languages like Python for automation.
• Experience in RTL design, chip bring-up, and post-silicon validation.
• Ability to adapt to a dynamic work environment and changing requirements.
• Team player with a positive attitude and willingness to learn.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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