SoC Verification Engineer – UVM, SV, Onsite

Links Technology Solutions, Inc.; Allentown (Lehigh County); Hybrid; USD 76,000 - 90,000; Full time

Job summary

Links Technology Solutions, Inc. in Allentown, PA is seeking an ASIC Verification Engineer to develop UVM-based verification environments and verification plans for SoC designs. You will implement assertions, traffic generators, agents, and scoreboards while collaborating across teams to ensure testability and robust verification.

The role requires 5–12 years of industry experience, strong SystemVerilog skills, and a drive to solve complex challenges in a fast-paced, onsite environment.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• UVM Based testbench development.
• Experience in ASIC or SOC verification.
• Developing test plans and verification infrastructure.
• Proficiency in SystemVerilog.
• Timing and gate level simulation experience.
• C coding for firmware delivery for post silicon bringup.
• Experience with formal verification techniques including abstraction and end-to-end checking.
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation.
• SystemVerilog coding and debug.
• AI based CAD efficiency improvisation initiatives.
• High speed serial protocols preferred UCIe, PCIe.
• Analog debug experience including DAC/ADC & calibrations white-box verification.

Responsibilities

• Develop and implement Universal Verification Methodology (UVM) based verification environments.
• Create comprehensive verification plans at both block and system levels.
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards.
• Collaborate with cross-functional teams to evaluate design testability and verification requirements.
• Lead debug efforts and provide solutions for complex technical challenges.

Skills

UVM Based testbench development

ASIC/SoC verification

Developing test plans & verification

SystemVerilog proficiency

Timing & gate-level simulation

C coding for firmware delivery

Formal verification techniques

SystemVerilog coding & debug

AI-based CAD efficiency initiatives

Analog debug: DAC/ADC & calibrations

UCIe/PCIe protocol experience

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Python

Perl

Scripting for automation

Job description

Links Technology Solutions, Inc. in Allentown, PA is seeking an ASIC Verification Engineer to develop UVM-based verification environments and verification plans for SoC designs. You will implement assertions, traffic generators, agents, and scoreboards while collaborating across teams to ensure testability and robust verification.

The role requires 5–12 years of industry experience, strong SystemVerilog skills, and a drive to solve complex challenges in a fast-paced, onsite environment.