SoC PV Engineer: Full-Chip Signoff & Tapeouts

Tenstorrent; United States; Hybride; USD 100 000 - 500 000; Plein temps

Résumé du poste

Tenstorrent is seeking a SoC Physical Design Verification Engineer to join our innovative team. This role, based in Santa Clara, CA, Austin, TX, or Fort Collins, CO, offers a hybrid work environment and requires driving full-chip signoff across various technology nodes.

We welcome candidates with 7–14 years of experience in CPU/IP/SoC physical verification and a BS/MS in Electrical/Electronics Engineering. Compensation ranges from $100k - $500k based on experience and location.

Qualifications

• 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Expertise in DRC, LVS, ERC verification using industry-standard tools.
• Strong understanding of advanced nodes and FinFET design challenges.

Responsabilités

• Drive full-chip signoff and ensure manufacturable, high-quality silicon.
• Lead physical verification closure and debug issues.
• Collaborate across RTL, PD, CAD, and packaging teams.

Connaissances

CPU/IP/SoC physical verification

Debugging skills

Collaboration across teams

Scripting in Python and TCL

Formation

BS/MS in Electrical/Electronics Engineering

Outils

Calibre

ICV

Pegasus

FC

Innovus

Description du poste

Tenstorrent is seeking a SoC Physical Design Verification Engineer to join our innovative team. This role, based in Santa Clara, CA, Austin, TX, or Fort Collins, CO, offers a hybrid work environment and requires driving full-chip signoff across various technology nodes.

We welcome candidates with 7–14 years of experience in CPU/IP/SoC physical verification and a BS/MS in Electrical/Electronics Engineering. Compensation ranges from $100k - $500k based on experience and location.