Full-Chip Physical Design Verification Engineer

Tenstorrent; Santa Clara (CA); Hybrid; USD 100,000 - 500,000; Full time

Benefits offered by this job

Highly competitive compensation package

Equal opportunity employer

Job summary

Tenstorrent in Santa Clara, CA is seeking a SoC Physical Design Verification Engineer to lead the signoff of high-quality silicon. The ideal candidate will have 7-14 years of experience in CPU/IP/SoC verification, proficiency with DRC, LVS, and advanced process technologies, as well as scripting skills in Python and TCL. This hybrid role allows for flexible work at other locations including Austin, TX, and Fort Collins, CO. Competitive compensation ranges from $100k to $500k based on qualifications and experience.

Qualifications

• 7-14 years of hands-on CPU/IP/SoC physical verification experience.
• Expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification.
• Strong background in ESD planning, padring integration, bump/RDL strategies.
• Solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design.

Responsibilities

• Drive full-chip signoff and ensure manufacturable, high-quality silicon.
• Lead physical verification closure (DRC, LVS, ERC, etc.).
• Collaborate across RTL, PD, CAD, and packaging teams.

Skills

CPU/IP/SoC physical verification

Debugging

Collaboration across teams

Leadership and mentoring

Scripting in Python and TCL

Education

BS/MS in Electrical/Electronics Engineering or related

Tools

Calibre

ICV

Pegasus

FC

Innovus

Job description

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high‑performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full‑chip signoff and ensure manufacturable, high‑quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast‑paced environment and enjoy solving complex challenges in cutting‑edge silicon, we’d love to hear from you.

This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands‑on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.

What We Need

• BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands‑on CPU/IP/SoC physical verification experience.
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry‑standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.).
• Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Scripting proficiency in Python and TCL for automation and flow optimization.

What You Will Learn

• Advanced physical verification methodologies and flow optimization for next‑generation SoCs.
• Integration and verification strategies for full‑chip signoff across advanced process technologies.
• Cross‑functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.