Lead Full-Chip PV Engineer

Celero Communications, Inc.; San Jose (CA); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. in San Jose, CA, is seeking a Principal Physical Verification Engineer to own all aspects of full-chip PV on advanced process nodes. You will collaborate with Analog and Physical Design teams to ensure tapeout readiness and high-quality DRC/LVS results.

The role requires 7+ years of PV experience, expertise with ICV/Calibre, and scripting skills in Tcl/Python. The position offers competitive base salary, strong growth, and exposure to cutting-edge 7nm/5nm tech.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications.
• Experience with Physical Verification tools such as IC Validator (ICV) and Calibre.
• Ability to assemble a flow to support block/chip level PV.
• Strong floorplanning skills to avoid DRC/LVS issues.
• Automation skills using Tcl, Python, or shell scripting.

Responsibilities

• Lead the full-chip Physical Verification effort.
• Own execution plans and schedules for full-chip PV.
• Drive quality, milestones, and tapeout readiness.
• Collaborate with analog and layout teams to ensure clean integration.
• Support tapeout readiness reviews.

Skills

Full-chip PV

Floorplanning

Automation scripting

Education

Bachelor's or Master's degree in Electrical Engineering or related field

Tools

Synopsys IC Validator (ICV)

Siemens Calibre

Job description

Celero Communications, Inc. in San Jose, CA, is seeking a Principal Physical Verification Engineer to own all aspects of full-chip PV on advanced process nodes. You will collaborate with Analog and Physical Design teams to ensure tapeout readiness and high-quality DRC/LVS results.

The role requires 7+ years of PV experience, expertise with ICV/Calibre, and scripting skills in Tcl/Python. The position offers competitive base salary, strong growth, and exposure to cutting-edge 7nm/5nm tech.