SoC Power & Thermal Modeling Architect — Platform (Equity)

Apple, Inc.

Cupertino (CA)

On-site

USD 216,000 - 325,000

Full time

Just now
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Benefits offered by this job

Comprehensive medical and dental
Retirement benefits
Discounted products and free services
Education expense reimbursement

Job summary

Apple, Inc. in Cupertino, CA, seeks a Power Performance Modeling Architect to join Platform Architecture. You will design and optimize constrained performance models for SoC power, thermal, and reliability, partnering with SoC, system and software architects.

You’ll drive simulator development, validate against real workloads, and influence future Apple products with high-visibility impact.

Qualifications

  • BS in Electrical or Computer Engineering or related engineering degree.
  • Experience in high-performance and low power microprocessor architecture and design techniques.
  • Experience coding in C, Python or similar programming languages.

Responsibilities

  • Build and maintain performance model under constrained power and thermals. Identify and prepare new workloads for analysis.
  • Work with architects and design teams to characterize workloads. Find opportunities to optimize product targets.
  • Work with control engineers to model and optimize the latest power, thermal and reliability control systems.
  • Work with system design engineers to guide the design of form factors.

Skills

High-performance architecture
Low power design
C programming
Python programming
Performance modeling

Education

BS in Electrical or Computer Engineering
MS or PhD in Electrical or Computer Engineering

Tools

Simulation tools

Job description

Apple, Inc. in Cupertino, CA, seeks a Power Performance Modeling Architect to join Platform Architecture. You will design and optimize constrained performance models for SoC power, thermal, and reliability, partnering with SoC, system and software architects.

You’ll drive simulator development, validate against real workloads, and influence future Apple products with high-visibility impact.

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