SoC Architecture and Design Engineer, Senior Member of Technical Staff (SMTS)

Micron Technology; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Benefits offered by this job

Bonuses and equity opportunities

Job summary

Micron Technology is seeking a SoC Architecture and Design Engineer in Folsom, CA. In this role, you will be responsible for architecting, designing, and integrating next-generation HBM SoC logic die. The ideal candidate will work closely with various teams to deliver high-performance solutions that meet power and performance targets.

The position requires a Bachelor's or master's degree in electrical engineering and a minimum of 15 years of experience. Proficiency in SystemVerilog and familiarity with SoC integration methodologies are essential.

Qualifications

• Minimum of 15 years of experience in relevant field.
• Familiarity with SoC integration methodologies is essential.
• Experience with high-speed interfaces and power management concepts.

Responsibilities

• Architect, design, and implement RTL for SoC-level blocks.
• Integrate internal and third-party IP in HBM logic die.
• Collaborate with cross-functional teams for manufacturable builds.

Skills

Proficiency in SystemVerilog/Verilog

Experience with RTL-to-GDS flow

Programming experience (Python, TCL, etc.)

Education

Bachelor’s or master's degree in electrical/computer engineering

Tools

EDA tools from Cadence

EDA tools from Synopsys

Job description

Job Overview

As a SoC Architecture and Design Engineer in the Heterogeneous Integration Group (HIG), you will architect, design, develop, and integrate next‑generation HBM SoC logic die. You will collaborate with architecture, design, verification, physical design, firmware, and product teams to deliver powerful, high‑performance SoC solutions that meet demanding power, performance, area, and schedule targets.

Key Responsibilities

• Architect, design, and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Architect and design memory sub‑systems, including memory IP selection and integration, bus and protocol selection, and power/performance/area optimisation.
• Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic).
• Translate architectural and micro‑architectural specifications into high‑quality RTL implementations.
• Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate cross‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Minimum Qualifications

• Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field, with a minimum of 15 years of experience.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and sign‑off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs.
• Familiarity with high‑speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).

Compensation

US base salary range: $177,000 - $334,000 per year.

Additional compensation may include bonuses and equity.

EEO Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.