HBM SoC RTL Design Engineer

Micron Technology; Folsom (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Micron Technology is looking for a SoC Design Engineer in Folsom, California, to contribute to next-generation HBM SoC logic die development. The role involves designing and implementing RTL for SoC-level blocks, collaborating with multi-functional teams, and participating in integration activities.

Candidates should have at least 10 years of experience in electrical or computer engineering and be proficient in SystemVerilog. Ideal candidates will also have experience with EDA tools and scripting.

Qualifications

• Minimum of 10 years of experience in a related field.
• Familiarity with RTL-to-GDS flow, synthesis, static timing analysis.
• Exposure to DFT concepts and debug.

Responsibilities

• Design and implement RTL for SoC-level blocks used in HBM logic die.
• Collaborate with SoC architects on specifications.
• Assist with pre-silicon validation and root-cause analysis.

Skills

SystemVerilog/Verilog

SoC integration methodologies

Programming or scripting (Python, TCL, Perl)

Education

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field

Tools

EDA tools (Cadence, Synopsys, Siemens)

Job description

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets.

Key Responsibilities

• Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die.
• Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic).
• Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations.
• Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi‑functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Minimum Qualifications

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field, with a minimum of 10 years of experience in a related field.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL‑to‑GDS flow, including synthesis, static timing analysis, and develop sign‑off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Preferred Qualifications

• Experience with HBM, DRAM, or memory‑centric SoC designs.
• Familiarity with high‑speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).

Equal Employment Opportunity

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.