SoC Microarchitecture Design Engineer

Intel Corporation; Santa Clara (CA); On-site; USD 106,000 - 173,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Vacation

Job summary

Intel Corporation is seeking a College Grad to join its AI SoC organization. You will design and simulate logic for cutting-edge SoCs, implement architecture features, and ensure design integrity through verification and optimization.

Participation spans RTL coding, IP integration, and collaboration with cross-functional teams. The role emphasizes secure design practices, performance-aware RTL optimization, and ongoing learning in a fast-paced, global AI hardware environment.

Qualifications

• Bachelor's or higher in Electrical/Computer Engineering with hands-on RTL design, internship or project experience.
• Proficiency in Verilog or VHDL RTL coding.
• Familiarity with synthesis, timing analysis, and power optimization.
• Knowledge of SoC and IP integration principles.

Responsibilities

• Develop logic design, RTL coding, and simulation for SoC designs.
• Define and implement architecture and microarchitecture features for logic blocks.
• Perform quality checks across RTL, timing, power, and design integrity.
• Optimize RTL for power, performance, area, and timing targets.
• Collaborate with IP providers to integrate and validate IPs at the SoC level.
• Review and contribute to verification plans and ensure features are tested.
• Identify and resolve RTL test failures to ensure feature correctness.
• Apply secure development practices addressing design security objectives.
• Drive QA compliance for IP and SoC handoff across the design flow.

Skills

RTL design

Verilog

VHDL

logic design

debugging

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical/Computer Engineering (optional)

Job description

Intel Corporation is seeking a College Grad to join its AI SoC organization. You will design and simulate logic for cutting-edge SoCs, implement architecture features, and ensure design integrity through verification and optimization.

Participation spans RTL coding, IP integration, and collaboration with cross-functional teams. The role emphasizes secure design practices, performance-aware RTL optimization, and ongoing learning in a fast-paced, global AI hardware environment.