SoC Architect & Silicon Bring-Up Engineer

OpenAI; San Francisco (CA); On-site; USD 287,000 - 485,000; Full time

Job summary

OpenAI is seeking a SoC Engineer to architect, design, and integrate first‑party AI accelerators. You will build processors, interconnects, and platform infra to connect accelerator designs into complete systems.

The role blends architectural judgment with hands‑on implementation, partnering with design, verification, firmware, and software teams from IP integration to post‑silicon debug. You will work across architecture, design, verification, physical design, and software to define interfaces

Qualifications

• Experience in SoC architecture, RTL design, and full‑chip integration through silicon bring‑up.
• Familiarity with Arm Cortex-M/A subsystems and AMBA protocols like AXI/APB.
• Experience with PCIe, high‑speed I/O, and die‑to‑die links.
• Ability to work across hardware, firmware, and software teams to define interfaces and boot behavior.

Responsibilities

• Define and implement SoC architectures spanning processors, interconnects, peripherals, PCIe and die‑to‑die interfaces.
• Develop microarchitecture and RTL for subsystems supporting I/O and SoC functionality.
• Integrate Arm cores, AXI/APB fabrics, and third‑party IP, including glue logic.
• Develop reset/boot architectures with firmware/software teams and ensure end‑to‑end validation.
• Drive debug, test, security integration and silicon bring‑up with design teams.

Skills

SoC architecture

RTL design

SystemVerilog

AMBA interconnects

embedded processors

hardware bring-up

debug & security

scripted automation

Tools

Arm Cortex-M

Arm Cortex-A

PCI Express

AXI/APB fabrics

SerDes/ PHY

RTL verification tools

Job description

OpenAI is seeking a SoC Engineer to architect, design, and integrate first‑party AI accelerators. You will build processors, interconnects, and platform infra to connect accelerator designs into complete systems.

The role blends architectural judgment with hands‑on implementation, partnering with design, verification, firmware, and software teams from IP integration to post‑silicon debug. You will work across architecture, design, verification, physical design, and software to define interfaces