SoC Memory Subsystem Architect for High-Performance Chips

Samsung Electronics; San Jose (CA); On-site; USD 151,000 - 252,000; Full time

Benefits offered by this job

Medical benefits

Free onsite lunch

401(k)

Job summary

Samsung Electronics’ System IP & SoC Architecture team at SARC/ACL is shaping memory subsystem designs for premium Exynos SoCs. The role focuses on defining and delivering advanced memory architectures, interfaces, and caches for high-performance mobile platforms.

You will collaborate across software, hardware, and validation teams to optimize memory performance, power, and area while staying current with JEDEC standards and emerging memory tech.

Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD
• Experience designing and developing complex digital systems and SoC memory architectures
• Strong understanding of memory hierarchies, memory interfaces (e.g., DDR, LPDDR, HBM), and memory controllers is crucial
• Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
• Knowledge of memory scheduling, bandwidth management, and latency optimization
• High familiarity with existing and emerging JEDEC memory standards
• Strong written and verbal communication skills
• Experience with cache coherence protocols and bus protocols (e.g., CHI, ACE, AXI) is a plus
• Experience with the Android ecosystem and analysis tools is a plus
• Experience with Arm architecture and ecosystem is a plus

Responsibilities

• Identify, propose, and deliver new SoC memory architectures and features for premium mobile and related product platforms.
• Contribute to high-impact deliverables, with the freedom to experiment and explore novel ideas to challenge existing norms and push the boundaries of what is possible.
• Create detailed designs and specifications for memory subsystems, including memory interfaces, controllers, and caches.
• Analyze PPA trade-offs and optimize memory subsystem performance, power consumption, and area utilization to meet system requirements.
• Work closely with software, hardware, and validation teams to ensure memory subsystem designs meet system requirements and are properly integrated
• Create and maintain detailed documentation of memory subsystem designs, including architecture, implementation, and verification plans.
• Stay up-to-date with emerging memory technologies and recommend their adoption in SoC designs.

Skills

SoC memory architectures

Memory hierarchies

Memory interfaces

Cache subsystems

Cache coherence protocols

Arm architecture

Android ecosystem

Communication skills

Education

Bachelor's in CS/Engineering

Master's degree

PhD

Tools

Analysis tools

Job description

Samsung Electronics’ System IP & SoC Architecture team at SARC/ACL is shaping memory subsystem designs for premium Exynos SoCs. The role focuses on defining and delivering advanced memory architectures, interfaces, and caches for high-performance mobile platforms.

You will collaborate across software, hardware, and validation teams to optimize memory performance, power, and area while staying current with JEDEC standards and emerging memory tech.