SOC Design Verification Engineer

Pyramid Consulting, Inc; United States; Remote; USD 103,000 - 117,000; Part time

Job summary

Pyramid Consulting, Inc. is seeking an experienced SOC Design Verification Engineer for a 6-month contract (remote, US). The role focuses on SoC verification, testbench development, and cross-functional collaboration to drive coverage and sign-off.

You will implement verification plans, integrate IPs, UVCs, VIPs, and perform GLS, UVM, and UPF-based low-power verification. Strong SystemVerilog skills and debugging are essential.

Qualifications

• Experience in SoC level verification and testbench development.
• Hands-on RTL debugging, integration, and coverage closure.
• Knowledge of UPF low-power verification and GLS debugging.
• Familiarity with JTAG or DAC verification is a plus.

Responsibilities

• Verify SoC at block and system level, drive verification execution and coverage closure.
• Develop and run SoC verification plans, testcases, and coverage models.
• Integrate IPs, UVCs, and VIPs into the verification environment.
• Drive power-aware verification and GLS simulations.
• Debug RTL, integration, and protocol issues.
• Collaborate with Design, DFT, Firmware, and Architecture teams for signoff.

Skills

SystemVerilog

UVM

SoC verification

Debugging

Automation

Tools

RAL modeling

Job description

Immediate need for a talented SOC Design Verification Engineer. This is a 06+ Months Contract opportunity with long-term potential and is located in US (Remote).

Job ID: 26-30161

Pay Range: $75 - $85/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).

Key Responsibilities:

• Responsible for SoC level verification, driving verification execution, integration, coverage closure, low-power verification, GLS, and test-chip validation activities.
• Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements.
• Integrate IPs, UVCs, and VIPs into the SoC verification environment.
• Drive functional/code coverage closure, power-aware verification, and Gate-Level Simulations (GLS).
• Perform debug of RTL, integration, protocol issues.
• RAL Modeling and verification.
• Own test-chip verification and collaborate with Design, DFT, Firmware, and Architecture teams for verification signoff.

Key Requirements and Technology Experience:

• Strong expertise in SystemVerilog, UVM, and SoC verification methodologies.
• Experience in testbench bring-up, SoC integration, and coverage-driven verification.
• Hands-on experience in RAL modeling and RAL-based register verification, including register access, mirroring, prediction, and functional coverage.
• Hands-on experience with UPF-based low-power verification and GLS debugging.
• Knowledge of JTAG, DAC, and analog/mixed-signal model verification.
• Strong debugging, automation, and stakeholder management skills.

Our client is a leading IT Industry and we are currently interviewing to fill this and other similar contract positions.

Pyramid Consulting, Inc. provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.