ASIC Design Verification Engineer, University Graduate, PhD, Machine Learning

Google; Sunnyvale (CA); On-site; USD 132,000 - 189,000; Full time

Job summary

A leading company is seeking an ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. This role involves verifying complex digital designs and collaborating with engineers to develop custom silicon solutions. Candidates should have a PhD and expertise in SystemVerilog. The position offers a competitive salary and the chance to contribute to innovative products used by millions worldwide.

Benefits

Bonus

Equity

Benefits

Qualifications

• Experience in verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience with verification methodology (e.g., UVM/OVM/VMM).

Responsibilities

• Create a constrained-random verification environment using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.

Skills

Problem Solving

Communication

Education

PhD in Electrical Engineering

PhD in Computer Engineering

PhD in Computer Science

Tools

SystemVerilog

UVM

Job description

ASIC Design Verification Engineer, University Graduate, PhD, Machine Learning

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info_outline X Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Madison, WI, USA; Sunnyvale, CA, USA. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Madison, WI, USA; Sunnyvale, CA, USA.

• PhD in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• Experience in verifying digital logic at RTL using SystemVerilog for ASICs.

Preferred qualifications:

• Experience with verification methodology (e.g., UVM/OVM/VMM).
• Experience with the full verification life cycle.
  
• Expertise in SystemVerilog.
• Excellent problem solving and communication skills, with the ability to be a team player.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Engineer, you will use your design and verification expertise to verify complex digital designs. You will collaborate closely with design and verification engineers in active projects and perform direct verification. Using your SystemVerilog coding and problem solving skills, you will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.

The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• Plan the verification of digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios.
  

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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