Silicon Validation & Characterization Intern (Fall, SJ)

Cadence; San Jose (CA); On-site; USD 55,000 - 95,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence DDR IP group is seeking a Post-Silicon Validation Engineering Intern in San Jose. The role focuses on validating system-level and electrical performance of internal silicon test chips, with close collaboration across analog and digital teams to debug issues and deliver characterization reports.

Ideal candidates are pursuing a BS or MS in electrical engineering, with strong fundamentals in analog/digital electronics, RTL, and signal integrity.

Qualifications

• Pursuing a Bachelor's or Master's in electrical engineering.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Experience in hardware semiconductor or electronics is a plus.
• Experience with script-based test automation in Python, C or other scripting tools is a plus.

Responsibilities

• Validate system-level and electrical performance of internal silicon test chips.
• Debug silicon issues with analog and digital design teams.
• Deliver high-quality characterization reports and drive testing efforts.

Skills

Communication

Analytical thinking

RTL

Signal integrity

Control systems

Python

C

Education

Bachelor's or Master's in Electrical Engineering

Tools

Python

C

Job description

Cadence DDR IP group is seeking a Post-Silicon Validation Engineering Intern in San Jose. The role focuses on validating system-level and electrical performance of internal silicon test chips, with close collaboration across analog and digital teams to debug issues and deliver characterization reports.

Ideal candidates are pursuing a BS or MS in electrical engineering, with strong fundamentals in analog/digital electronics, RTL, and signal integrity.