Intern Characterization and Support Fall 2026

Cadence; San Jose (CA); On-site; USD 55,000 - 95,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence DDR IP group is seeking a Post-Silicon Validation Engineering Intern in San Jose. The role focuses on validating system-level and electrical performance of internal silicon test chips, with close collaboration across analog and digital teams to debug issues and deliver characterization reports.

Ideal candidates are pursuing a BS or MS in electrical engineering, with strong fundamentals in analog/digital electronics, RTL, and signal integrity.

Qualifications

• Pursuing a Bachelor's or Master's in electrical engineering.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Experience in hardware semiconductor or electronics is a plus.
• Experience with script-based test automation in Python, C or other scripting tools is a plus.

Responsibilities

• Validate system-level and electrical performance of internal silicon test chips.
• Debug silicon issues with analog and digital design teams.
• Deliver high-quality characterization reports and drive testing efforts.

Skills

Communication

Analytical thinking

RTL

Signal integrity

Control systems

Python

C

Education

Bachelor's or Master's in Electrical Engineering

Tools

Python

C

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. (local candidates will be considered)

Intern will be responsible for validating both system-level and electrical performance of internal silicon test chips. The role includes debugging silicon issues in close collaboration with analog and digital design teams, and delivering high-quality characterization reports. The intern will work cross-functionally to ensure product functionality, reliability, and successful deployment. The candidate is expected to be strongly motivated by the prospect of driving system and electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same. Very good fundamentals in analog and digital electronics, RTL, Signal integrity, control systems. Strong analytical and problem-solving skills

Requirements

Currently pursuing a Bachelor's or Master's degree in electrical engineering with 0-2 years of relevant work experience Excellent written and verbal communication skills Ability to work collaboratively in a team environment Prior experience in the hardware semiconductor or electronics industry is a plus Experience with script-based test automation in Python, C or other scripting tools is a plus.

As this role is expected to be employed in San Jose during the Fall semester, applicants should ideally be attending a local school. Candidate should be able to prove they can work fulltime hours in San Jose during the Fall. Also need to have legal authorization to work in the US.

The annual salary range for California is $40/hr to $69/hr. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

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