Post-Silicon Validation Intern: Characterization & Debug

Cadence Design Systems; San Jose (CA); On-site; USD 55,000 - 95,000; Full time

Job summary

Cadence Design Systems in San Jose, California, offers an on-site internship in the DDR IP group as a Post-Silicon Validation Engineering Intern. The role emphasizes validating chip performance, debugging silicon issues, and delivering characterization reports while collaborating across analog and digital teams.

Ideal candidates are pursuing a Bachelor's or Master's in EE with 0-2 years of experience, possess strong communication, and can work full-time on-site during the Fall.

Qualifications

• Pursuing a Bachelor's or Master's in electrical engineering with 0-2 years of relevant work experience.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Prior experience in the hardware semiconductor or electronics industry is a plus.
• Experience with script-based test automation in Python, C or other scripting tools is a plus.

Responsibilities

• Validate system-level and electrical performance of internal silicon test chips.
• Debug silicon issues in collaboration with analog and digital design teams.
• Deliver high-quality characterization reports.

Skills

Communication

Team collaboration

Hardware industry experience

Python scripting

C programming

Education

Pursuing Bachelor's or Master's in Electrical Engineering

Tools

Python

C

Job description

Cadence Design Systems in San Jose, California, offers an on-site internship in the DDR IP group as a Post-Silicon Validation Engineering Intern. The role emphasizes validating chip performance, debugging silicon issues, and delivering characterization reports while collaborating across analog and digital teams.

Ideal candidates are pursuing a Bachelor's or Master's in EE with 0-2 years of experience, possess strong communication, and can work full-time on-site during the Fall.