Silicon Physical Design Engineer V - ASIC Power Engineer

Spectraforce Technologies, Inc.; Raleigh (NC); On-site; USD 140,000 - 210,000; Full time

Job summary

Spectraforce Technologies, Inc. seeks a highly experienced Silicon Physical Design Engineer V focused on ASIC power to optimize power estimates and back-end implementations for AR/VR products.

The role emphasizes scripting, data analysis, and integration of PPRTL/Prime Power flows. Remote work in PST time zone is offered, with 10+ years of relevant experience and a BS in Electrical Engineering or Computer Science required.

Qualifications

• 10+ years of experience in ASIC power engineering or CAD/physical design
• Experience with power estimation tools and synthesis, some physical design
• Knowledge of power trade-offs in design and back-end implementation
• Hands-on experience in scripting, data analysis

Responsibilities

• Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power).
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform analyses.
• Correlate RTL-level power estimates against gate-level sign-off power; explain deltas.
• Produce per-block/ per-hierarchy power breakdowns and identify top power contributors.

Skills

Power estimation

Power-aware design

Scripting & data analysis

Education

BS in Electrical Engineering/Computer Science

Tools

Synopsys PPRTL

PTPX/Prime Power

Verdi power analysis

PowerArtist

Job description

Job Title: Silicon Physical Design Engineer V - ASIC Power Engineer

Location: Remote in PST time zone

Duration: 12 months initially, with the potential for extension up to 2 years.

Job Description

• ASIC Power Engineer to perform power analysis and optimizations in ASIC for Client's AR/VR products.
• Areas of interests includes Machine Learning. Primary languages are Python, TCL and System Verilog.

Must-Have Skills

1. Experience with power estimation tools and synthesis, some physical design
2. Knowledge of power trade-offs in design and back-end implementation
3. Hands-on experience in scripting, data analysis

Nice-to-have Skills

1. Hands-on experience with Synopsys PPRTL, PTPX/Prime Power, Verdi based power analysis and debug.
2. Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle, leakage).
3. Strong scripting: TCL, Python and Excel based scripting and data-post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments.

Years of Experience

10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer

Degrees/Certifications Required

• BS in Electrical Engineering/Computer Science or equivalent experience

Responsibilities

• Set up and maintain PPRTL and PTPX power analysis flows (average and time-based/peak power).
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations; handle long-waveform and windowed analysis.
• Correlate RTL-level power estimates against gate-level signoff power and explain deltas.
• Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste.
• Recommend and evaluate power reduction opportunities (clock gating efficiency, datapath gating, memory power, idle leakage).
• Automate flows and reporting with TCL, Python, and Make-based build systems; integrate into regression/CI.
• Document methodology and support design teams in interpreting results.
• Perform PPA optimization with Fusion compiler.
• Perform RTL and netlist level Power analysis
• Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
• Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing).
• Implement some blocks at RTL and UPF
• Ability to document and communicate clearly

Minimum Qualifications

• 10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer
• Experience with power estimation tools and synthesis, some physical design
• Knowledge of power trade-offs in design and back end implementation
• Hands-on experience in scripting, data analysis
• BS in Electrical Engineering/Computer Science or equivalent experience

Preferred Qualifications

• Hands-on production experience with Synopsys (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence (Joules), PowrArtist
• Ability to debug simulation-to-power flow issues end to end.
• Strong scripting: TCL, Python and Excel based scripting and data-post-processing tools, model fitting, data visualization and analysis; comfortable with Linux and large compute/job-scheduling environments.
• Experience in low power design, tools and methodologies including power intent UPF specifications Silicon Power Characterization
• Some power modeling/profiling experience at IP/SoC level

Interview Process

How many rounds of interviews? 1-2 zoom interviews

Types of Interviews

1. Power Analysis & Low Power Methodology
2. Scripting (Optional)

Interview Duration

45 mins