Silicon/Hardware Tech Program Manager - Lead Chip Programs

MatX; Mountain View (CA); On-site; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO (accrued)

12 company holidays

up to 3 weeks remote work

Health insurance (employee & dependets

Dental & Vision insurances

Life insurance

Professional development budget

Team meals onsite

Commute on us

AI resources

Job summary

MatX seeks a Technical Program Manager for its Silicon/Hardware team in Mountain View to drive end-to-end silicon programs from concept to tapeout. You will coordinate Architecture, RTL Design, and DV, managing milestones, risks, and cross-functional reviews across multiple engineering teams.

We value 15+ years in chip/IC development and strong PM discipline, with proficiency in Jira, GitHub, Confluence, Smartsheet, MS Project, and Google Workspace.

Qualifications

• 15+ years in chip/IC development as an engineer, engineering manager, or technical program manager

Responsibilities

• Lead end-to-end execution of Silicon HW development programs from concept through production.
• Partner with Architecture, RTL Design, and DV to identify bottlenecks and mitigate risks before tapeout.
• Define core operational processes and stage-gate reviews for smooth transitions from architecture to implementation and verification.
• Develop playbooks and best practices for program management across the Silicon HW org.
• Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs.
• Track dependencies, risks, milestones, and escalation paths; ensure tapeout readiness.

Skills

Chip/IC development

Technical PM

Cross-functional leadership

RTL DV milestones

Schedule management

Executive communications

Jira/GitHub/Confluence

Vendor coordination

Tools

Jira

GitHub

Confluence

Smartsheet

MS Project

Google Workspace

Job description

MatX seeks a Technical Program Manager for its Silicon/Hardware team in Mountain View to drive end-to-end silicon programs from concept to tapeout. You will coordinate Architecture, RTL Design, and DV, managing milestones, risks, and cross-functional reviews across multiple engineering teams.

We value 15+ years in chip/IC development and strong PM discipline, with proficiency in Jira, GitHub, Confluence, Smartsheet, MS Project, and Google Workspace.