Technical Program Manager, Silicon/Hardware

MatX Inc.; Mountain View, Northern (CA, KY); Hybrid; USD 180,000 - 240,000; Full time

Job summary

MatX Inc. is building a high-performance Silicon HW platform for GenAI in Mountain View.

The Technical Program Manager will own cross-functional execution from planning to tapeout, coordinating Architecture, RTL Design, DV, and tapeout readiness across multiple engineering teams. You will drive milestones, manage risks, develop stage-gate reviews, and establish playbooks for program management within the Silicon HW organization.

Qualifications

• 15+ years of chip/IC development experience required.
• At least 3 years in a technical program manager role.
• Experience delivering silicon programs from concept to tapeout.
• Ability to manage cross-functional teams and external vendors.
• Fluent understanding of SoC or chiplet design flows and milestones.

Responsibilities

• Lead end-to-end Silicon HW program execution from concept through production.
• Coordinate Architecture, RTL Design, and DV to hit tapeout milestones.
• Define stage-gate processes and drive cross-functional reviews.
• Create playbooks and best practices for program management in Silicon HW.
• Support tradeoffs on performance, power, area, and manufacturability.
• Escalate risks and provide timely updates to leadership.
• Track dependencies, risks, owners, and milestones.

Skills

Chip/IC development

Technical program management

Cross-functional leadership

SoC design knowledge

Tapeout planning

Job description

What MatX Is Building

MatX is on a mission to be the compute platform for Artificial General Intelligence. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest Machine Learning workloads for Artificial General Intelligence.

MatX is seeking a Technical Program Manager to join our Silicon/Hardware team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for this role will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

About the Role

You will own the cross-functional execution framework for advanced Silicon HW programs, from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.

What You'll Do Here

• Lead end-to-end execution of Silicon HW development programs, from concept through production, driving planning and implementation across cross-functional teams.




• Partner tightly with Architecture, RTL Design, and Design Verification (DV) teams to identify bottlenecks, track coverage metrics, and mitigate risks before they impact the tapeout schedule.




• Define the core operational processes and modes of work for the HW group, building and refining the stage-gate reviews required to transition smoothly from architecture into implementation and verification.




• Develop playbooks and best practices for program management across the Silicon HW organization for cross-functional deliveries.




• Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs.




• Track technical dependencies, schedule risks, owners, closure dates, critical path, program milestones, tapeout readiness, silicon bring-up deliverables, and escalation paths.




• Manage technical risks related to schedule, design maturity, IP readiness, verification closure, physical signoff, package/test readiness, and supply chain.




• Act as a liaison between hardware teams and company leadership, providing clear, timely updates and insights.

Who you are

• 15+ years of experience in chip/IC development as an engineer, engineering manager, or technical program manager, with at least 3 years in a technical program manager role.




• Experience leading Silicon HW programs through multiple phases of the silicon lifecycle, with end-to-end chip execution from concept to silicon.




• Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and tight schedules.




• Technical fluency in SoC or chiplet design flows — enough to understand RTL milestones, DV signoff, Silicon HW handoffs, and silicon bring-up phases without needing translation.




• Strong technical judgment with the ability to manage tradeoffs across performance, power, area