Technical Program Manager, Silicon/Hardware

Jobtailor; Mountain View (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Jobtailor in Mountain View, CA seeks a seasoned Technical Program Manager to lead cross-functional Silicon hardware programs from concept to production. You will own the execution roadmap, coordinate architecture, RTL, and verification, and drive milestones, risks, and tapeout readiness with multiple engineering teams.

The role requires 15+ years in chip development and 3+ years in a technical program manager capacity, with strong communication skills and governance capabilities across schedules

Qualifications

• 15+ years of experience in chip/IC development
• At least 3 years in a technical program manager role
• Experience leading Silicon HW programs through multiple silicon lifecycle phases
• Experience coordinating cross-functional engineering teams and vendors
• Technical fluency in SoC or chiplet design flows (RTL milestones, DV signoff, silicon bring-up)
• Strong judgment on performance, power, area, cost, schedule, and risk
• Ability to drive schedules, dependencies, issue tracking, risk management, and executive updates
• Experience coordinating design reviews and driving closure across teams
• Excellent written and verbal communication skills
• Authorized to work in the United States and capable of compliance with export control laws
• Bonus: AI infrastructure, datacenter racks, networking/storage systems, or rack-scale validation
• Bonus: high-speed interconnects, liquid-cooled systems, telemetry, diagnostics
• Bonus: BE PD hands-on engineering experience

Responsibilities

• Own the cross-functional execution framework for advanced Silicon HW programs from planning through tapeout
• Drive milestones, dependencies, reviews, risk management, and tapeout readiness across engineering teams
• Lead end-to-end execution of Silicon HW development from concept to production
• Partner with Architecture, RTL Design, and Verification to identify bottlenecks and mitigate risks
• Define operational processes and modes of work for the HW group
• Build stage-gate reviews for transitions from architecture to implementation and verification
• Develop playbooks and best practices for program management across the organization
• Support silicon planning across performance, power, area, cost, reliability, and manufacturability trades
• Track dependencies, schedules, owners, closure dates, critical path, milestones, and escalation paths
• Liaise with hardware teams and leadership, providing clear updates and insights

Skills

Cross-functional leadership

Project management

Risk management

Executive communication

Strong written communication

Tools

Jira

GitHub

Confluence

Smartsheet

MS Project

Google Workspace

Job description

• Own the cross-functional execution framework for advanced Silicon HW programs from early planning through tapeout
• Drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams
• Lead end-to-end execution of Silicon HW development programs from concept through production
• Drive planning and implementation across cross-functional teams
• Partner with Architecture, RTL Design, and Design Verification teams to identify bottlenecks, track coverage metrics, and mitigate risks
• Define operational processes and modes of work for the HW group
• Build and refine stage-gate reviews for transition from architecture into implementation and verification
• Develop playbooks and best practices for program management across the Silicon HW organization
• Support silicon planning across performance, power, area, cost, reliability, and manufacturability tradeoffs
• Track technical dependencies, schedule risks, owners, closure dates, critical path, program milestones, tapeout readiness, silicon bring-up deliverables, and escalation paths
• Manage risks related to schedule, design maturity, IP readiness, verification closure, physical signoff, package/test readiness, and supply chain
• Liaise between hardware teams and company leadership, providing clear and timely updates and insights

Requirements

• 15+ years of experience in chip/IC development as an engineer, engineering manager, or technical program manager
• At least 3 years in a technical program manager role
• Experience leading Silicon HW programs through multiple phases of the silicon lifecycle, with end-to-end chip execution from concept to silicon
• Experience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and tight schedules
• Technical fluency in SoC or chiplet design flows, including RTL milestones, DV signoff, Silicon HW handoffs, and silicon bring-up phases
• Strong technical judgment managing tradeoffs across performance, power, area, cost, schedule, quality, and risk
• Ability to drive schedules, dependency management, issue tracking, risk management, milestone governance, and executive-level communication
• Experience coordinating design reviews and driving closure across cross-functional engineering teams
• Strong written and verbal communication skills
• Proficiency with Jira, GitHub, Confluence, Smartsheet, MS Project, Google Workspace, or equivalent
• All candidates must be authorized to work in the United States
• Ability to perform job functions in compliance with U.S. export control laws without obtaining a license
• Bonus: experience with AI infrastructure, datacenter racks, networking systems, storage systems, or high-power server platforms
• Bonus: experience with high-speed interconnects, liquid-cooled systems, telemetry, diagnostics, or rack‑scale validation
• Bonus: prior hands‑on engineering experience in BE PD

Core Competencies

Demonstrates extensive experience in managing cross-functional Silicon HW programs, driving execution from concept through production while ensuring compliance with performance, power, area, and cost tradeoffs. Proficient in risk management, milestone governance, and effective communication with engineering teams and leadership.

Highest-signal resume keywords

• Silicon HW Program Management
• Technical Program Management
• Cross‑Functional Team Leadership
• Risk Management
• SoC Design Flow Expertise

ATS Optimization Keywords

Hard Skills

• Chip Development
• Silicon Lifecycle Management
• Dependency Management
• Issue Tracking
• Milestone Governance
• Performance Tradeoffs
• Power Tradeoffs
• Area Tradeoffs
• Cost Tradeoffs
• Quality Management

Soft Skills

• Strong Written Communication
• Strong Verbal Communication

Industry Keywords

• Silicon HW
• SoC
• Chiplet Design
• Silicon Bring‑Up
• High‑Speed Interconnects
• Datacenter Racks
• Networking Systems
• Storage Systems
• Liquid‑Cooled Systems
• Rack‑Scale Validation

Tools & Technologies

• Jira
• GitHub
• Confluence
• Smartsheet
• MS Project
• Google Workspace