Silicon Engineer for AI Hardware Co-Design

Anthropic; San Francisco (CA); Hybrid; USD 320,000 - 485,000; Full time

Benefits offered by this job

Equity donation matching

Generous vacation

Parental leave

Flexible working hours

Nice office in San Francisco

Job summary

Anthropic in San Francisco seeks a senior hardware leader to help build a custom silicon team, spanning strategy, specification, and execution with clock-speed decisions and collaboration across inference, performance, kernels, and infrastructure groups.

The role requires shipping silicon and operating with high autonomy in a fast-moving program, with a realistic schedule and strong design authority to drive consequential outcomes.

Qualifications

• Deep hands-on expertise in at least one silicon domain from the list.
• Direct personal contribution to silicon that tape-out and shipped.
• Fluent understanding of adjacent domains to reason about chip tradeoffs.
• Experience with external partners and maintaining a technical bar.
• Track record of owning directional technical decisions.

Responsibilities

• Take part in end-to-end program activities: strategy, specification, execution, and technical bar.
• Write specifications and interface definitions for others to implement.
• Make directional calls on technology/IP selection and build-vs-license decisions.
• Develop AI-assisted approaches to code-like parts of your domain.
• Contribute to architecture discussions from your domain perspective.
• Collaborate with inference, performance, kernels, and infrastructure teams on co-design.
• Support first-silicon bring-up and debug across domains.

Skills

Front-end verification

Pre-silicon verification

Physical design

Design for test

Analog and mixed-signal

Technology and foundry

CAD and design infrastructure

Packaging, signal integrity

Education

Bachelor's degree

Job description

Anthropic in San Francisco seeks a senior hardware leader to help build a custom silicon team, spanning strategy, specification, and execution with clock-speed decisions and collaboration across inference, performance, kernels, and infrastructure groups.

The role requires shipping silicon and operating with high autonomy in a fast-moving program, with a realistic schedule and strong design authority to drive consequential outcomes.