Silicon Correlation Engineer - CPU Timing & Debug

Apple Inc.; Santa Clara (CA); On-site; USD 90,000 - 110,000; Full time

Benefits offered by this job

Employee stock purchase plan

Relocation assistance

Educational expense reimbursement

Job summary

Apple Inc. in Santa Clara, CA is seeking a Senior CPU Implementation Silicon Correlation Engineer to validate and correlate pre-silicon design targets with silicon performance.

The role focuses on ensuring frequencies, voltages, and power targets are realizable on silicon and in final products shipped to customers. You will obtain silicon measurement data, analyze timing runs, and work with post-silicon teams to assess ROI of design features while diagnosing root causes from post-silicon speed

Qualifications

• BS degree and 10+ years of relevant industry experience.
• Experience with a chip tapeout of a custom or PnR block.
• Experience with STA and spice simulations.

Responsibilities

• Obtain process-related silicon measurement data from product and technology teams.
• Analyze pre-silicon timing runs to understand margins and relate to silicon parameters.
• Work with post-silicon teams evaluating ROI of design features and methodologies.
• Analyze post-silicon speed debug data to identify root causes of failing paths.

Skills

STA timing analysis

Spice simulations

Data parsing & plotting

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering

Tools

ATPG pattern framework

Job description

Apple Inc. in Santa Clara, CA is seeking a Senior CPU Implementation Silicon Correlation Engineer to validate and correlate pre-silicon design targets with silicon performance.

The role focuses on ensuring frequencies, voltages, and power targets are realizable on silicon and in final products shipped to customers. You will obtain silicon measurement data, analyze timing runs, and work with post-silicon teams to assess ROI of design features while diagnosing root causes from post-silicon speed