Silicon Power & SoC Characterization Engineer

Apple Inc.; Cupertino (CA); On-site; USD 150,000 - 218,000; Full time

Benefits offered by this job

Stock purchase plan

Employee stock program

Medical coverage

Dental coverage

Tuition reimbursement

Relocation assistance

Job summary

Apple Inc. in Cupertino seeks an Electrical Engineer to validate and optimize operating voltages for SoCs. You will collaborate with cross-functional teams and use JMP Pro 17 to analyze data and plot graphs guiding design decisions.

You’ll contribute to test planning for SoCs, perform measurements affecting power and performance, and help characterize test setups. Sign-off on silicon characterization with design, validation, and manufacturing ensures robust production screening.

Qualifications

• Master’s degree in Electrical Engineering or related field.
• Strong foundation in PDN, power integrity and Vmin effects.
• Experience with data exploration, statistics, and data summarization.
• Knowledge of SRAM/memory design, test and characterization.
• Experience with Python, Perl, or JSL.
• Familiarity with circuit schematic/ layout and PERC.

Responsibilities

• Coordinate with cross functional teams to validate and compute optimal operating voltages for different SoC.
• Use JMP Pro 17 to process data from different teams, conduct statistical analyses and plot graphs.
• Support test plans for different SoCs and characterize test setups.
• Perform measurements that impact Soc power and performance for next generation products.
• Drive data reviews and sign off on silicon characterization activities.

Skills

Electrical engineering

Vmin

Power integrity

Data analysis

SoC

Test planning

PDN

Memory design

Sram

Circuit design

JMP Pro

Education

Master’s degree in Electrical Engineering

Tools

Python

Perl

JSL

Job description

Apple Inc. in Cupertino seeks an Electrical Engineer to validate and optimize operating voltages for SoCs. You will collaborate with cross-functional teams and use JMP Pro 17 to analyze data and plot graphs guiding design decisions.

You’ll contribute to test planning for SoCs, perform measurements affecting power and performance, and help characterize test setups. Sign-off on silicon characterization with design, validation, and manufacturing ensures robust production screening.