SerDes IP Architect — High-Speed Analog/DSP Innovator

Apple, Inc.; Cupertino (CA); On-site; USD 129,000 - 225,000; Full time

Benefits offered by this job

Stock programs

Relocation assistance

Education reimbursement

Healthcare benefits

Job summary

Apple, Inc. in Cupertino seeks a self-motivated SERDES Micro Architect to drive the definition of next-generation analog mixed-signal IPs for Apple silicon, enabling breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch.

You will define the microarchitecture of analog mixed-signal IPs with emphasis on SERDES design, review firmware and circuits, verify performance, and lead debugging during system bring-up while collaborating with signal integrity teams.

Qualifications

• Bachelor's degree required.
• Strong background in SERDES design and high-speed signaling.
• Experience leading high-speed SERDES receiver/transmitter and clocking blocks.
• Experience with adaptation/optimization algorithms.
• Knowledge of communications and information theory.
• Proficiency in DSP concepts.
• Familiarity with Python/MATLAB/C/C++ for modeling.
• Firmware or embedded software experience is a plus.

Responsibilities

• Define the microarchitecture of analog mixed-signal IPs with emphasis on SERDES design.
• Review firmware code, analog and digital circuits and verify performance to meet requirements.
• Lead debug efforts in system bring-up and factory test.
• Collaborate with signal integrity engineers to define system requirements.

Skills

SerDes design

High-speed interfaces

Adaptation algorithms

Communications theory

DSP concepts

Mixed-signal modeling

Machine learning basics

Firmware/embedded

Education

Bachelor's degree

Tools

Python

MATLAB

C/C++

Job description

Apple, Inc. in Cupertino seeks a self-motivated SERDES Micro Architect to drive the definition of next-generation analog mixed-signal IPs for Apple silicon, enabling breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch.

You will define the microarchitecture of analog mixed-signal IPs with emphasis on SERDES design, review firmware and circuits, verify performance, and lead debugging during system bring-up while collaborating with signal integrity teams.