SerDes Micro Architect

Apple Inc.; Beaverton (OR); On-site; USD 180,000 - 240,000; Full time

Job summary

Apple Inc. is seeking a self-motivated SERDES Micro Architect to drive the definition of next-generation analog mixed-signal IPs for Apple silicon, delivering breakthroughs in power and performance.

You will define microarchitecture, review firmware and circuits, verify performance, lead system bring-up debugging, and collaborate with silicon evaluation, design verification, and signal integrity teams to ensure robust designs. Experience in high-speed SERDES and mixed-signal modeling is required.

Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.

Responsibilities

• You will define the Micro Architecture of analog mixed‑signal IPs with emphasis on SERDES design.
• You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements.
• You will work with silicon evaluation and design verification teams to define expected behavior.
• You would lead the debug effort in system bring up and factory test.
• You will work with signal integrity engineers to determine system requirements.

Job description

Analog Mixed-Signal (AMS) Team is seeking a self‑motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering breakthrough power and performance for iPhone, iPad, Mac, and Apple Watch.

Description

You will define the Micro Architecture of analog mixed‑signal IPs with emphasis on SERDES design. You will review firmware code, analog and digital circuits and will verify that the design meets performance requirements. You will work with silicon evaluation and design verification teams to define expected behavior. You would lead the debug effort in system bring up and factory test. You will work with signal integrity engineers to determine system requirements.

Minimum Qualifications

• BS degree in technical discipline with minimum 10 years of relevant experience.

Preferred Qualifications

• Experience leading the definition of high‑speed SERDES receiver, transmitter, and clocking blocks.
• Deep understanding of adaptation and optimization algorithms.
• Deep understanding of communications and information theory.
• Proficiency in equalizers, timing recovery and system identification.
• Proficiency in DSP concepts and applications.
• Familiarity with mixed‑signal modeling in Python/MATLAB/C/C++.
• Experience in system design and performance tradeoff.
• Familiarity with simulation tools for analog, digital, and/or mixed‑signal circuits.
• Familiarity with Machine Learning concepts.
• Experience in firmware or embedded software development is a plus.

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