Senior Wireless Mixed-Signal Modeling & Verification Engineer

Apple Inc.; San Francisco (CA); On-site; USD 185,000 - 325,000; Full time

Benefits offered by this job

Employee stock plan

RSU awards

Employee Stock Purchase Plan

Comprehensive medical and dental cover

Retirement benefits

Discretionary bonuses

Relocation assistance

Tuition reimbursement

Discounted products and services

Job summary

Apple Inc. in Cupertino and the San Francisco Bay Area hosts a leading hardware modeling team focused on analog/RF and mixed-signal verification for wireless SoCs. You will develop behavioral models in SystemVerilog, build test benches and checkers, and work with emulation platforms to ensure first-silicon readiness.

Strong collaboration across teams and clear communication are essential. Ideal applicants bring a BS with 10+ years, expertise in real-number modeling, knowledge of PLLs and

Qualifications

• BS in Electrical Engineering or related field with 10+ years of experience in hardware modeling.
• Hands‑on experience in Mixed‑Signal Verification and Real Number modeling.
• Knowledge of wireless technologies (WiFi, BT, UWB) and analog circuits (PLLs, LDOs, Bandgap, ADC/DAC).
• Excellent communication and problem‑solving skills.

Responsibilities

• Develop accurate, simulation‑efficient analog behavioral models for Analog/RF blocks in SystemVerilog.
• Build and reuse monitors and checkers for RF, Mixed‑Signal and Digital blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking.
• Write scripts for automation of the flow and improve Mixed‑Signal verification methodology.
• Develop models that are emulation ready.

Skills

SystemVerilog modeling

Analog/RF/Mixed‑Signal

Mixed‑Signal Verification

Testbench development

Python scripting

SystemC/C++

Education

BS in Electrical Engineering

Master’s or PhD preferred

Tools

SystemC

C/C++

Python

Perl

Job description

Apple Inc. in Cupertino and the San Francisco Bay Area hosts a leading hardware modeling team focused on analog/RF and mixed-signal verification for wireless SoCs. You will develop behavioral models in SystemVerilog, build test benches and checkers, and work with emulation platforms to ensure first-silicon readiness.

Strong collaboration across teams and clear communication are essential. Ideal applicants bring a BS with 10+ years, expertise in real-number modeling, knowledge of PLLs and