Senior Wireless IC Digital Design Engineer (Staff)

Analog Devices

Dallas (TX)

On-site

USD 120,000 - 170,000

Full time

14 days+
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Job summary

Analog Devices, Inc. is seeking a Senior Staff Wireless IC Digital Designer to lead RF/wireless digital design across medical, energy, and embedded security IC programs. You will guide product definition, RF system and circuit design, and software implementation throughout silicon development.

Expertise in wireless system digital design, bit-level modeling, and production-ready flow is required. The role involves defining SoC, system, and block‑level verification plans, performing RTL design and

Qualifications

  • Defined complex digital system architectures and led engineering teams.
  • Experience driving digital design methodologies and process improvements.
  • Collaborated across product, test, and manufacturing teams to meet schedules.

Responsibilities

  • Support development of product requirements and specifications.
  • Analyze and develop SoC architectures to meet Power, Performance & Area goals.
  • Perform RTL design and integration of RFIC architectures.
  • Conduct RTL and gate-level simulations for verification at block and SoC levels.
  • Oversee physical design and FPGA verification for Radio IP before tape out.
  • Assist in transferring ICs to production with Product and Test teams.

Skills

System Architecture
Technical Leadership
Multi‑Domain Expertise
Methodology Expertise
Cross‑Functional Collaboration
Customer Engagement

Education

Master's/PhD in Electrical Engineering
8–12 years in digital design

Job description

Analog Devices, Inc. is seeking a Senior Staff Wireless IC Digital Designer to lead RF/wireless digital design across medical, energy, and embedded security IC programs. You will guide product definition, RF system and circuit design, and software implementation throughout silicon development.

Expertise in wireless system digital design, bit-level modeling, and production-ready flow is required. The role involves defining SoC, system, and block‑level verification plans, performing RTL design and

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