Senior Verification Engineer - SystemVerilog/UVM

SGS Consulting; Sacramento (CA); On-site; USD 110,000 - 140,000; Full time

Job summary

SGS Consulting in Sacramento is seeking a verification engineer to own electrical verification of complex systems. You will lead test plan development, implement scalable verification infrastructure, and report coverage and bug status with cross-functional teams.

Required skills include SystemVerilog, UVM, Python, and C/C++, plus 5–10 years of verification experience and a Bachelor's degree in EE or CS. On-site in California is expected.

Qualifications

• Bachelor's degree in electrical engineering, computer science, or equivalent.
• 5-10 years of experience as a verification engineer.

Responsibilities

• Define electrical verification methodologies for different systems with researchers, architects, and design teams.
• Define and track detailed test plans for modules and top-level systems.
• Architect, design, and drive scalable test infrastructure implementation.
• Track coverage metrics and bugs encountered and fixed.
• Own execution, interpretation, and reporting of verification work status and results.
• Support system bring-up and debug activities.
• Clearly communicate test plans and results.

Skills

SystemVerilog

UVM

Python

C/C++

Debugging

Verification

Education

Bachelor's degree in Electrical Engineering or Computer Science

Job description

SGS Consulting in Sacramento is seeking a verification engineer to own electrical verification of complex systems. You will lead test plan development, implement scalable verification infrastructure, and report coverage and bug status with cross-functional teams.

Required skills include SystemVerilog, UVM, Python, and C/C++, plus 5–10 years of verification experience and a Bachelor's degree in EE or CS. On-site in California is expected.