Technical Staff Engineer - Verification

Microchip Technology Inc; Chandler (AZ); On-site; USD 91,000 - 232,000; Full time

Job summary

Microchip Technology Inc in Chandler, AZ is seeking an experienced verification engineer to verify next‑generation, highly secure, low‑power FPGA device products. The role emphasizes constrained random and formal verification, reusable UVM environments, and collaboration with architecture and design teams.

You will work across RTL, power-aware, and post-silicon debug, leveraging AI/ML-driven verification and cross‑functional teams. Mentoring junior engineers is part of the responsibilities.

Qualifications

• 12+ years in functional verification of complex SoC designs.
• Expertise in SystemVerilog, UVM, formal verification methodologies.
• Proven experience in methodology development and tool automation.
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Good understanding of SoC architectures - ARM/RISC-V.
• Experience with at least two of: CPU subsystems, PCIe Gen3/Gen4/Gen5, DDR4/DDR5, LPDDR4X, MIPI DSI/CSI, Ethernet MAC, USB, Security/IPs.
• Exposure to emulation, hardware prototyping and post-silicon debug; FPGA-based acceleration.
• Python, TCL/TK, and C/C++ for automation and validation.
• Familiarity with Siemens/Cadence/Synopsys verification suites; Git/Perforce/SVN.

Responsibilities

• Verify complex subsystems and SoCs using constrained random, formal and C-based verification.
• Develop and maintain reusable UVM test benches and environments.
• Involve in RTL, power-aware and gate-level verification.
• Contribute to quality by using AI/ML-enabled verification methodologies.
• Collaborate with emulation and hardware prototyping teams to define a unified verification approach.
• Collaborate with architecture and design teams for first-silicon success.
• Mentor junior team members.

Skills

SystemVerilog

UVM

Formal verification

Tool automation

AI/ML-driven EDA

SoC architectures

CPU subsystems

PCIe Gen3/4/5

DDR4/DDR5

MIPI CSI/DSI

Ethernet MAC

USB

Security IPs

Emulation

Scripting (Python)

Git

Perforce

SVN

Cadence/Siemens/Synopsys

Education

BS/MS in Electrical Engineering

Tools

Git

Perforce

SVN

Cadence/Siemens/Synopsys tools

Job description

Job Description

The FPGA Business Unit of Microchip Technology Inc is seeking an experienced and innovative verification engineer for our team in Chandler, Arizona to work on the verification of our next generation, highly secure, low-power FPGA device products.

Key Responsibilities

• Verification of complex subsystems and SoC using an optimal combination of constrained random, formal and C based verification methodologies.
• Develop and maintain highly reusable UVM based test benches and verification environments.
• Involve in RTL, power aware and gate level verification.
• Contribute to quality and productivity by using AI/ML-enabled verification methodologies.
• Collaborate with emulation and hardware prototyping teams to define a unified verification methodology.
• Collaborate with architecture and design teams to ensure seamless execution and first‑silicon success.
• Mentor junior team members.

Requirements / Qualifications

• 12+ years in functional verification of complex SoC designs
• Expertise in System Verilog, UVM, formal verification methodologies
• Proven experience in methodology development and tool automation.
• Familiarity with AI/ML-driven EDA tools and scripting for flow integration.
• Good understanding of SoC architectures - ARM/RISC-V
• Expertise in at least two of the following domains/peripherals
  • CPU subsystems
  • PCIe Gen3/Gen4/Gen5
  • DDR4/DDR5, LPDDR4X
  • MIPI DSI/CSI
  • Ethernet MAC
  • USB
  • Security and cryptography IPs.
• Exposure to emulation, hardware prototyping and post‑silicon debug
  • Experience with FPGA‑based acceleration platforms and simulation/emulation flows.
• Software & Scripting
  • Python, TCL/TK, and C/C++ for automation and validation.
• Tools
  • Familiarity with Siemens/Cadence/Synopsys verification suites
  • Revision control systems (Git, Perforce, svn).
• Excellent debug skills
• Experience working with global cross functional teams
• Excellent communication and collaboration skills

Preferred Skills

• Highly Desirable: Strong understanding of FPGA architecture
• Experience with coverage-driven verification using ML-based optimizations.
• Experience in emulation, hardware prototyping and post-silicon debug,
• Knowledge and exposure to complete SOC RTL to GDS to silicon release flow.

Required Education

• BS or MS in Electrical/Electronic Engineering with 12+ years of experience

Travel Time

0% - 25%

Physical Attributes

Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements

80% sitting, 10% walking, 10% standing

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position, which could be performed in the US, is $91,000 - $232,000.*
*Range is dependent on numerous factors including job location, skills and experience.

Equal Employment Opportunity

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.