Senior Verification Engineer - Remote, AI-Driven Contract

System One; El Segundo (CA); Remote; USD 179,000 - 183,000; Full time

Benefits offered by this job

Health benefits

401(k) plan

Dental & Vision coverage

Job summary

System One is seeking a Senior Verification Engineer to own verification planning and execution for complex ASIC/SoC blocks from test plan through sign-off. The role requires SystemVerilog/UVM or formal verification, plus metric-driven verification and RTL/debug experience.

The position is a 6-month contract, on-site relocation to Southern CA (El Segundo) or Austin, TX, or remote option. Compensation is $130–$133 per hour, with extensions possible and opportunities to advance in verification

Qualifications

• Bachelor's degree or 7+ years in ASIC/SoC verification.
• Hands-on SystemVerilog/UVM or formal testbench development.
• Metric-driven verification with coverage closure.

Responsibilities

• Own verification planning and execution for complex blocks from test plan to sign-off.
• Translate design specs into verification strategies with measurable coverage goals.
• Choose verification methods including constrained-random, formal analysis, and directed testing.
• Develop environments, scoreboards, monitors, coverage components, and assertions.
• Drive coverage closure, regression health, and sign-off readiness across sims and formal results.
• Build verification infra, regression/CI, and reuse strategy across IP, subsystem, and SoC levels.
• Apply AI-assisted verification for stimulus generation, regression triage, and coverage analytics.
• Review testbench architecture and mentor junior engineers in verification methodology.

Skills

SystemVerilog

UVM

Formal verification

Constrained-random testing

RTL/SoC verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

7+ years equivalent experience

Job description

System One is seeking a Senior Verification Engineer to own verification planning and execution for complex ASIC/SoC blocks from test plan through sign-off. The role requires SystemVerilog/UVM or formal verification, plus metric-driven verification and RTL/debug experience.

The position is a 6-month contract, on-site relocation to Southern CA (El Segundo) or Austin, TX, or remote option. Compensation is $130–$133 per hour, with extensions possible and opportunities to advance in verification