Senior Design Verification Engineer

Cirrus Logic; Chandler (AZ); On-site; USD 100,000 - 145,000; Full time

Job summary

A prominent silicon technology company in Arizona seeks an experienced Design Verification Engineer to join its team. This role involves collaborating with digital and analog designers to ensure high-quality mixed-signal IC solutions. Candidates should have a Bachelor’s, Master’s, or PhD in Electrical Engineering or related fields, with relevant experience in ASIC verification and HDLs like Verilog and SystemVerilog. The position offers a rigorous working environment with opportunities to advance verification methodologies.

Qualifications

• 5+ years of experience in relevant roles, or 3+ years with a Master’s, or none required with a PhD.
• Experience in silicon design and/or ASIC verification is essential.
• Hands-on experience with testbench architecture and stimulus generation required.

Responsibilities

• Develop comprehensive verification plans based on design requirements.
• Perform functional verification at block and chip level.
• Design and implement UVM-based testbenches and maintain them.

Skills

Verilog

SystemVerilog with UVM

Digital design principles

ASIC verification

Testbench architecture

Coverage analysis

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related

Master’s degree

PhD

Tools

Regression execution tools

Mixed-signal ASIC verification tools

Job description

For over four decades, Cirrus Logic has been propelled by top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end‑user solutions for the world’s top consumer brands. Cirrus Logic is also known for its award‑winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!

We are seeking an experienced and innovative Design Verification Engineer to join a world‑class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high‑quality mixed‑signal IC solutions. You will be responsible for end‑to‑end functional verification across block‑level and chip‑level designs, contributing to advanced verification methodologies and infrastructure.

This position offers exposure to multiple verification domains including UVM‑based testbench development, formal verification, hardware emulation/acceleration, gate‑level simulations, and software‑driven verification in a highly collaborative and technically rigorous environment.

Responsibilities

• Develop comprehensive verification plans aligned with design and system requirements.
• Perform functional verification of custom mixed‑signal ASICs at block and chip level.
• Design and implement UVM‑based testbenches, including infrastructure, scoreboards, checkers, and assertions.
• Create directed and constrained‑random test suites to ensure robust functional coverage.
• Implement, analyze, and drive functional and code coverage, including coverage closure.
• Conduct failure analysis, regression triage, and debug, resolving functional and timing‑related issues.
• Run and debug gate‑level simulations, including timing violations and back‑annotation issues.
• Develop and maintain digital and mixed‑signal behavioral models to support verification.
• Support verification flow and infrastructure development, including regressions and automation.
• Collaborate cross‑functionally with digital/analog design, systems, applications, firmware/software, and manufacturing test teams.
• Contribute to both pre‑silicon verification and post‑silicon validation efforts.
• Proactively improve verification methodologies, processes, and best practices.

Required Knowledge, Skills, and Experience

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Bachelor’s with 5+ years of relevant experience.
  • Master’s with 3+ years of relevant experience.
  • PhD with 0+ years of relevant experience.
• Significant industry experience in silicon design and/or ASIC verification.
• Strong proficiency with HDLs: Verilog and/or VHDL.
• Strong proficiency with HVLs: SystemVerilog with UVM (or OVM/AVM/Vera).
• Solid understanding of digital design principles and system architecture.
• Hands‑on experience with:
  • Testbench architecture and stimulus generation.
  • Regression execution and debug.
  • Coverage analysis and closure.
• Ability to work effectively in a cross‑disciplinary, team‑oriented environment.

Preferred Knowledge, Skills, and Experience

• Experience verifying mixed‑signal ASICs in complex SoC environments.
• Knowledge of signal processing concepts relevant to mixed‑signal designs.
• Experience with SystemVerilog Assertions (SVA).
• Exposure to or hands‑on experience with:
  • Formal verification.
  • Hardware emulation or acceleration.
  • Software‑driven verification.
• Demonstrated ability to evaluate, debug, and improve verification flows and methodologies.

Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.

Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job‑related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.