Senior Verification Engineer - High-Speed Coherent Hub (Equity)

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA is seeking a motivated Senior Verification Engineer to join our Tegra SoC IP Verification team. You will define verification strategies, develop robust environments, and drive coverage closure for high-speed interconnect IP in multi-chip platforms.

You will collaborate across architecture, design, FPGA, emulation, software and post-silicon teams, with opportunities to influence signoff and system validation. The role requires 3+ years ASIC verification and strong SystemVerilog/UVM skills.

Qualifications

• BS / MS or equivalent experience.
• 3+ years of ASIC verification experience with complex IPs or SoC subsystems.
• Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification methodologies.
• Experience developing verification environments, checkers, assertions, and functional coverage.
• Strong debugging and problem-solving skills with industry-standard simulation and debug tools.

Responsibilities

• Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus.
• Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other key IP features.
• Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
• Develop and complete performance test plans to validate bandwidth, latency, QoS, and other performance requirements.
• Drive functional and code coverage closure and provide to verification signoff.
• Debug complex RTL and verification issues and work closely with architecture and design teams to drive them to resolution.
• Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up.

Skills

SystemVerilog

UVM

Constrained-random

Coverage-driven

Debugging

Python

Shell

Education

BS/MS or equivalent

Tools

BFMs

Monitors

Assertions

Scoreboards

Job description

NVIDIA is seeking a motivated Senior Verification Engineer to join our Tegra SoC IP Verification team. You will define verification strategies, develop robust environments, and drive coverage closure for high-speed interconnect IP in multi-chip platforms.

You will collaborate across architecture, design, FPGA, emulation, software and post-silicon teams, with opportunities to influence signoff and system validation. The role requires 3+ years ASIC verification and strong SystemVerilog/UVM skills.