Senior ASIC Verification Engineer: Impact & Equity

NVIDIA Corporation; Westford (MA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation seeks a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for GPUs and SOCs. This role uses UVM, SystemVerilog and DV methodologies to ensure correctness across IP and sub-systems. You will collaborate with architects, designers and verification teams.

The base salary ranges for Level 3 and Level 4 are disclosed, with equity and benefits available. Applications close by August 22, 2026.

Qualifications

• Bachelor's or Master's degree (or equivalent) with relevant verification experience.
• Strong background in SystemVerilog/UVM verification at IP/sub-system level.
• Experience verifying interconnect protocols (Ethernet, USB, SATA).
• Proficient in debugging, analytical reasoning and problem solving.

Responsibilities

• Verify ASIC design, architecture, gold models and micro-architecture of HSIO controllers (Ethernet, NVLink) using UVM.
• Create reusable BFMs, monitors and scoreboards with coverage-driven verification.
• Define verification scope, develop test plans and verification infrastructure.
• Collaborate with architects, designers and pre-/post-silicon teams to complete tasks.

Skills

SystemVerilog

UVM

DV methodologies

IP verification

Analytical skills

Communication

Education

Bachelor's/Master's degree

Tools

Python

Perl

Simulation tools

Job description

NVIDIA Corporation seeks a Senior Design Verification Engineer to verify the design and implementation of High Speed I/O controllers for GPUs and SOCs. This role uses UVM, SystemVerilog and DV methodologies to ensure correctness across IP and sub-systems. You will collaborate with architects, designers and verification teams.

The base salary ranges for Level 3 and Level 4 are disclosed, with equity and benefits available. Applications close by August 22, 2026.