Senior Verification Engineer - High-Speed Coherent Hub

NVIDIA Corporation; Town of Montana (WI); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Hybrid work model

Job summary

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Verification Engineer to join the Tegra SoC IP Verification team. You will build robust verification environments, drive coverage and sign-off, and verify high-speed interconnect IP across complex multi-chip interfaces.

You will collaborate with architecture, design, FPGA, emulation, software, and post-silicon teams, and contribute to validation and silicon bring-up. Requires 3+ years ASIC verification and SV/UVM expertise.

Qualifications

• BS/MS or equivalent experience in EE/CS.
• 3+ years of ASIC verification experience with complex IPs or SoC subsystems.
• Strong background in SystemVerilog, UVM, constrained-random verification, and coverage-driven verification.
• Experience developing verification environments, checkers, assertions, and functional coverage.
• Strong debugging and problem-solving skills with experience using industry-standard simulation and debug tools.

Responsibilities

• Develop and maintain verification infrastructure, including testbenches, BFMs, checkers, monitors, scoreboards, assertions, and constrained-random stimulus.
• Define, review, and complete verification test plans for coherency protocol, ordering, error handling, performance, and other key IP features.
• Verify protocol compliance and interoperability across complex SoC and multi-chip interfaces.
• Develop and complete performance test plans to validate bandwidth, latency, QoS, and other performance requirements.
• Drive functional and code coverage closure and provide to verification signoff.
• Debug complex RTL and verification issues and work closely with architecture and design teams to drive them to resolution.
• Collaborate with FPGA, emulation, software, and post-silicon teams to support system validation and silicon bring-up.

Skills

SystemVerilog

UVM

Constrained-random verification

Coverage-driven verification

Debugging skills

Scripting (Python, Perl, Shell)

Education

BS / MS or equivalent experience

Tools

Simulation tools

Job description

NVIDIA Corporation in Santa Clara, CA is seeking a Senior Verification Engineer to join the Tegra SoC IP Verification team. You will build robust verification environments, drive coverage and sign-off, and verify high-speed interconnect IP across complex multi-chip interfaces.

You will collaborate with architecture, design, FPGA, emulation, software, and post-silicon teams, and contribute to validation and silicon bring-up. Requires 3+ years ASIC verification and SV/UVM expertise.