Junior Verification Engineer - DRAM Controller IP (Hybrid)

Rambus.com; Hillsboro (OR); Hybrid; USD 112,000 - 186,000; Full time

Job summary

Rambus is hiring a junior/design verification engineer to join the DRAM Controller IP team in Hillsboro, Oregon. The role focuses on pre-silicon RTL verification across DDR/LPDDR/HBM and graphics/GDDR controller technologies.

The position offers a hybrid work model with on-site collaboration and some remote work, reporting to the onsite Controller IP Verification director. A Bachelor’s in EE/CS and SystemVerilog/UVM experience are preferred.

Qualifications

• Bachelors Degree or above in EE/CS, project experience related to HDL logic Design-Verification
• SystemVerilog and/or UVM testbench, Verilog/SystemVerilog logic design/RTL familiarity/project work
• Pre-existing Experience / familiarity with one or more I/O controller technologies such as USB, SATA/SAS, Ethernet, Graphics/Display, or DDR/DRAM is desirable
• Working experience with Python and TCL scripting languages preferred

Responsibilities

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Skills

SystemVerilog

UVM

Verilog

Python

TCL scripting

Testbench development

DDR/DRAM familiarity

Education

Bachelor's Degree in EE/CS

Tools

Verilog/SystemVerilog

Python scripting

TCL scripting

Job description

Rambus is hiring a junior/design verification engineer to join the DRAM Controller IP team in Hillsboro, Oregon. The role focuses on pre-silicon RTL verification across DDR/LPDDR/HBM and graphics/GDDR controller technologies.

The position offers a hybrid work model with on-site collaboration and some remote work, reporting to the onsite Controller IP Verification director. A Bachelor’s in EE/CS and SystemVerilog/UVM experience are preferred.