Senior TPU Design Engineer— ML Hardware

Google; Mountain View (CA); On-site; USD 156,000 - 229,000; Full time

Job summary

Google is seeking a TPU Design Engineer, Silicon in Mountain View, CA. This mid-level role focuses on driving progress in digital design and mentoring junior engineers while contributing to cutting-edge silicon for on-device ML and data-center inference.

Required: a Bachelor's in EE/CS or related field and 5 years in digital logic, RTL, and Verilog/SystemVerilog, with knowledge of synthesis for low-power designs. Strong collaboration and leadership are expected.

Qualifications

• Bachelor's degree in a relevant field or equivalent practical experience.
• 5 years of experience with digital logic design principles, RTL design concepts, and Verilog/SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power; low-power design techniques.

Responsibilities

• Use simulation/emulation/power analysis tools to ensure power and performance meet specs.
• Develop, implement, and maintain design blocks and hardware subsystems.
• Collaborate with Verification and Silicon Validation teams for functionality.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Take a leadership role on technical project teams and set direction.

Skills

Digital logic design

RTL design concepts

Verilog

SystemVerilog

Power optimization

Low-power design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Google is seeking a TPU Design Engineer, Silicon in Mountain View, CA. This mid-level role focuses on driving progress in digital design and mentoring junior engineers while contributing to cutting-edge silicon for on-device ML and data-center inference.

Required: a Bachelor's in EE/CS or related field and 5 years in digital logic, RTL, and Verilog/SystemVerilog, with knowledge of synthesis for low-power designs. Strong collaboration and leadership are expected.