Senior SystemVerilog Verification Engineer (UVM)

Arrow Enterprise Computing Solutions; United States; On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Medical, Dental, Vision Insurance

401k with Matching Contributions

Disability Insurance

Health Savings Account (HSA) Options

Paid Time Off

Tuition Reimbursement

Growth Opportunities

Job summary

Arrow Enterprise Computing Solutions is seeking an experienced verification engineer to build scalable testbenches using UVM and SystemVerilog. The role focuses on constrained-random testing, coverage closure, and gate-level verification to ensure robust power-up and timing behavior.

You will plan verification from architectural specs, automate regression runs, and work with Cadence Xcelium or other major simulators.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong DV fundamentals and verification methodologies.
• Experience with constrained-random verification and assertions (SVA).
• Knowledge of AMBA AXI/AHB/APB protocols preferred.

Responsibilities

• Testbenches: Build scalable verification environments using UVM and SystemVerilog.
• Planning: Create detailed verification plans from architectural specifications.
• Execution: Write, run, and debug constrained-random and directed tests.
• Coverage: Define, measure, and close functional and code coverage metrics.
• Gate-Level: Run gate-level simulations to verify power-up and timing states.
• Automation: Develop scripts to automate regression runs and triage failures.

Skills

DV fundamentals

MMU verification

SRAM/memory subsystem verification

AXI bus protocols

DSP verification

Education

Bachelor's or Master's in EE/CE or related field

Tools

Cadence Xcelium

Synopsys VCS

Siemens Questa

Job description

Arrow Enterprise Computing Solutions is seeking an experienced verification engineer to build scalable testbenches using UVM and SystemVerilog. The role focuses on constrained-random testing, coverage closure, and gate-level verification to ensure robust power-up and timing behavior.

You will plan verification from architectural specs, automate regression runs, and work with Cadence Xcelium or other major simulators.