Senior System-Level Testability Engineer: AI Validation

Nvidia Corporation in; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Silicon Co-Design Group seeks a Senior System Level Testability Engineer to define and drive system-level diagnostics and post-silicon validation for complex chips. You will shape SLT production coverage, validate on silicon, and translate requirements into robust test coverage with hands-on lab bring-up.

You will collaborate across HW teams, define test infrastructure needs, and improve production workflows using AI to drive impact while managing risk.

Qualifications

• Bachelor's or Master's degree in Microelectronics, Electrical, Electronic or Computer Engineering or equivalent experience.
• 8+ years of relevant industry experience.
• Strong EE fundamentals: digital design, signal integrity, timing analysis, fault analysis, sampling, computer architecture.
• Strong data analysis skills; experience with volume data is a plus.
• Hands-on lab experience with silicon bring-up and lab debug.
• Knowledge of firmware/driver structures and their interaction with HW.
• Proven problem-solving, debugging, analysis, and logical reasoning with examples.
• Experience with Python, Bash, Linux.

Responsibilities

• Define and drive system-level diagnostics, verification, and post-silicon validation for semiconductor chips.
• Define SLT production coverage specifications and correlate to test coverage.
• Prototype and fine-tune speed, power, performance, yield, and quality on pre-production silicon.
• Develop and maintain system-level testing flows and link findings to design.
• Create KPIs to evaluate new tests and drive process improvements.

Skills

Python

Bash

Linux

System-level testability

Debugging

Data analysis

Firmware/driver interaction

Education

Bachelor's or Master's in Microelectronics/Electrical/Electronic/Computer Engineering

Tools

Lab bring-up

Job description

NVIDIA's Silicon Co-Design Group seeks a Senior System Level Testability Engineer to define and drive system-level diagnostics and post-silicon validation for complex chips. You will shape SLT production coverage, validate on silicon, and translate requirements into robust test coverage with hands-on lab bring-up.

You will collaborate across HW teams, define test infrastructure needs, and improve production workflows using AI to drive impact while managing risk.