Senior Low-Power Silicon Validation & AI-Driven Debug

NVIDIA Corporation

Santa Clara, Northern (CA, KY)

Hybrid

USD 168,000 - 311,000

Full time

4 days ago

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Job summary

NVIDIA Silicon Co-Design Group is seeking a versatile engineer to advance low-power silicon validation and system bring-up for AI and accelerated computing platforms. You will collaborate across silicon architecture, platform validation, firmware, telemetry, and productization to scale validation with AI analytics and automated workflows.

You will define power and performance strategies, build telemetry-driven analytics, and develop scalable observability and debug tools.

Qualifications

BS/MS in EE, CE, CS, Systems Engineering or equivalent experience.
10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies.
Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization.
Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.
Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics, or data-driven debug infrastructure.
Experience applying AI/ML or LLM technologies to silicon validation, telemetry analytics, workload optimization, or debug automation.
Background in platform power management technologies such as S0ix, ASPM, RTD3, Memory Self Refresh, or system-level power-state coordination.
Experience building large-scale telemetry pipelines, automated validation dashboards, or intelligent observability infrastructure.
Strong Python, data analytics, and automation framework development experience.
Experience working across architecture, firmware, silicon validation, and manufacturing organizations to drive production readiness.

Responsibilities

Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies.
Build intelligent workload characterization frameworks that use telemetry, behavioural clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle.
Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout.
Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques.
Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation.
Partner closely with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon platforms.
Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies.
Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release.