Director, System-Level Testing — Drive High-Volume Validation

Nvidia Corporation in; Santa Clara (CA); On-site; USD 272,000 - 426,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Director of System Level Testing to lead end-to-end post-silicon validation, test architecture, and manufacturing ramp for AI, data center, SOC and Tegra lines.

You will guide a team across design validation through high-volume production, collaborating with design, test, reliability, and manufacturing to drive yield and test optimization. Strong CMOS and mixed-signal expertise required; 15+ years in semis with 5+ in leadership. Equity and benefits included.

Qualifications

• 15+ years in semiconductor product development, testing, or manufacturing engineering.
• 5+ years in director-level leadership overseeing large cross-functional teams.
• Strong CMOS, analog/mixed-signal understanding and test experience.

Responsibilities

• Lead and mentor a team of product development engineers responsible for validation, characterization, and production ramp of NVIDIA product lines.
• Drive product development strategy from early silicon validation through qualification and high-volume manufacturing.
• Develop and implement validation methodologies and test strategies for mixed-signal silicon designs.
• Partner with design, test, reliability, and manufacturing teams for smooth design-to-production transitions.
• Oversee product characterization of new IC designs.
• Lead root-cause analysis and problem resolution related to silicon performance and yield.

Skills

CMOS expertise

System-level testing

Leadership

Cross-functional collaboration

Statistical analysis

High-volume manufacturing

SerDes validation

Yield analysis

Education

Master's or PhD in Electrical Engineering / Physics / Computer Engineering

Tools

JMP

Job description

NVIDIA is seeking a Director of System Level Testing to lead end-to-end post-silicon validation, test architecture, and manufacturing ramp for AI, data center, SOC and Tegra lines.

You will guide a team across design validation through high-volume production, collaborating with design, test, reliability, and manufacturing to drive yield and test optimization. Strong CMOS and mixed-signal expertise required; 15+ years in semis with 5+ in leadership. Equity and benefits included.