Senior System-Level Testability Engineer (Hybrid + Equity)

NVIDIA Gruppe; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Job summary

NVIDIA's Silicon Co-Design Group in Santa Clara seeks a Senior System Level Testability Engineer to join the TMRQ team. You will define and drive system-level diagnostics, verification, and post-silicon validation for complex chips, translating product requirements into effective test coverage.

The role requires hands-on lab experience with system-level post-silicon bring-up, debugging, and collaboration across hardware teams.

Qualifications

• Bachelor's or Master's Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience.
• 8+ years of relevant industry experience.
• Strong EE fundamentals, knowledgeable in digital design, signal integrity, statistics, timing analysis, fault analysis, sampling and computer architecture.
• Strong data analysis skills. Prior experience working with volume data is a plus.
• Validated hands-on lab experience with silicon bring-up and lab debug.
• Good understanding of firmware/driver structures and their interaction with HW.
• Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it
• Experience with Python, BASH, Linux

Responsibilities

• Partner with other HW engineering teams such as Silicon design and characterization teams, IO design and validation teams, system feature owners, Production Operations to determine coverage needs and constraints to resolve appropriate test conditions, diagnostic contents for production line screen.
• Define requirements to SW and board teams to support and improve test infrastructure, debug knobs and data collection features needed to support manufacturing screens effectively.
• Co-design testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on system-level test
• Prototype and fine-tune speed, power, performance, yield, and quality on pre-production silicon.
• Co-design , develop, and maintain system-level testing flows and incorporate takeaways from silicon and correlate to design.
• Define procedures to facilitate correlation activities between production testing infrastructure and internal diagnostic programs
• Support customer facing and quality teams during customer escalations to understand the issue and fix gaps identified in coverage.
• Create key performance indicators used to evaluate the effectiveness of the new tests.
• Initiate and drive process improvements and preventative actions through root cause analysis.

Skills

Python

BASH

Linux

Data analysis

Education

Bachelor's or Master's in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent

Tools

Linux

Job description

NVIDIA's Silicon Co-Design Group in Santa Clara seeks a Senior System Level Testability Engineer to join the TMRQ team. You will define and drive system-level diagnostics, verification, and post-silicon validation for complex chips, translating product requirements into effective test coverage.

The role requires hands-on lab experience with system-level post-silicon bring-up, debugging, and collaboration across hardware teams.