Senior/Staff SoC Design Verification Lead

Powerlattice Technologies Inc.; Vancouver (WA); Hybrid; USD 160,000 - 190,000; Full time

Benefits offered by this job

Stock option grant

Comprehensive benefits package

Hybrid work model

Job summary

Powerlattice Technologies Inc. is seeking an experienced Design Verification Lead to drive verification for complex SoC/IP designs. You will craft scalable SystemVerilog environments, implement coverage-driven verification, and lead RTL through gate-level validation with cross-functional teams.

The role emphasizes automated regression, CDC verification, clock-domain testing, and regression flow optimization using Xcelium and VCS, with leadership over a team of verification engineers.

Qualifications

• Bachelor's or Master's degree in electrical/computer engineering or related field.
• 10+ years of digital verification experience in SoCs with ownership of subsystems or full-chip verification.
• Solid understanding of digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration.
• Proficiency with AMBA, I2C, I3C, SPI, JTAG, and OBI protocols.
• Expertise in Verilog, SystemVerilog, UVM, and class-based verification methodologies.

Responsibilities

• Lead verification planning and execution for complex digital and mixed-signal subsystems, including defining verification strategies; test scenarios; coverage goals; and signoff criteria.
• Architect, develop, and maintain SystemVerilog-based verification environments and reusable verification infrastructure.
• Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.
• Develop reusable verification components and test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
• Perform RTL and gate-level simulation, including GLS and timing verification, to identify functional and timing issues.

Skills

SystemVerilog

UVM

RTL verification

Constrained-random

Python scripting

Verilog

Clock Domain Crossing

Debugging

Testbench development

Industry protocols

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

Synopsys tools

Cadence tools

Xcelium

VCS

Job description

Powerlattice Technologies Inc. is seeking an experienced Design Verification Lead to drive verification for complex SoC/IP designs. You will craft scalable SystemVerilog environments, implement coverage-driven verification, and lead RTL through gate-level validation with cross-functional teams.

The role emphasizes automated regression, CDC verification, clock-domain testing, and regression flow optimization using Xcelium and VCS, with leadership over a team of verification engineers.