Lead Design Verification Engineer (Hybrid)

RiseMe; Vancouver (WA); Hybrid; USD 160,000 - 190,000; Full time

Benefits offered by this job

Stock option grant

Health, dental, vision, and 401(k)

Job summary

Powerlattice is seeking a Senior/Staff Design Verification Lead to headline verification for complex SoC/IP designs. You will design scalable SystemVerilog environments, drive coverage and signoff, and collaborate across RTL, analog, and silicon validation teams.

Responsibilities include developing testbenches, constrained-random tests, CDC verification, and UVM-based infrastructure. 3 days onsite in Vancouver, WA or Chandler, AZ with possible remote flexibility for exceptional candidates.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• 10+ years of digital verification experience for SoCs with ownership of subsystems or full-chip verification.
• Solid understanding of digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration.
• Proficiency with industry-standard protocols: AMBA, I2C, I3C, SPI, JTAG, and OBI.
• Strong expertise in Verilog, SystemVerilog, UVM and class-based verification methodologies.
• Experience with constrained-random, coverage-driven verification, regression automation and signoff.
• SystemVerilog Assertions (SVA) and formal verification techniques.
• Scripting with Python, Perl, and UNIX shell for automation.
• Hands-on experience developing testbenches, drivers, monitors, scoreboards, and reusable verification IP.

Responsibilities

• Lead verification planning and execution for complex digital and mixed-signal subsystems, defining verification strategies, test scenarios, coverage goals, and signoff criteria.
• Architect, develop, and maintain SystemVerilog-based verification environments and reusable infrastructure.
• Develop directed, constrained-random, regression, and corner-case tests to verify functional requirements and design specifications.
• Create reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces.
• Perform CDC verification for async and sync clock-domain interfaces and develop UVM-based infrastructure and RAM/RA-like models where applicable.
• Develop checkers, scoreboards, reference models, assertions, and functional coverage to verify design behavior.
• Perform RTL and gate-level simulation with SDF-annotated GLS to identify functional and timing issues.
• Develop and optimize regression and GLS flows using Xcelium and VCS.
• Analyze functional and code coverage to drive closure and identify verification gaps.
• Debug complex RTL, testbench, simulation, and gate-level failures using waveform/log analysis.
• Collaborate with RTL, analog, architecture, and silicon validation teams to reproduce issues and drive resolution.
• Review specifications/RTL to identify corner cases, interface issues, and functional gaps.
• Translate silicon validation findings into simulation-based verification scenarios and regression tests.
• Provide technical leadership and mentorship to a team of verification engineers.

Skills

SystemVerilog

UVM

Verilog

SVA

Constrained-random

Coverage-driven

Python

Perl

UNIX/Linux

CDC

I2C/I3C

SPI

JTAG

OBI

AMBA

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Synopsys

Cadence

Job description

Powerlattice is seeking a Senior/Staff Design Verification Lead to headline verification for complex SoC/IP designs. You will design scalable SystemVerilog environments, drive coverage and signoff, and collaborate across RTL, analog, and silicon validation teams.

Responsibilities include developing testbenches, constrained-random tests, CDC verification, and UVM-based infrastructure. 3 days onsite in Vancouver, WA or Chandler, AZ with possible remote flexibility for exceptional candidates.