Senior Staff PHY RTL/DSP Engineer — SerDes DSP Expert

Credo; San Jose (CA); On-site; USD 160,000 - 250,000; Full time

Job summary

Credo is seeking a Senior Staff PHY RTL Design Engineer at its San Jose, CA headquarters to lead RTL architecture, design, implementation and verification of SerDes DSP blocks for high-performance networking and data center products.

The ideal candidate has strong RTL development experience with SystemVerilog and a solid background in high-speed SerDes architectures, ASIC flows, and debugging. Onsite role with comprehensive compensation and bonus eligibility.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field, with eight or more years of digital design experience (or equivalent expertise for senior candidates).
• Strong RTL development skills using SystemVerilog, including fixed-point arithmetic RTL implementation.
• Experience designing high-speed communication or DSP hardware.
• Experience with the ASIC development flow (e.g., Lint, CDC/RDC, synthesis, timing analysis) and familiarity with EDA tools from Synopsys, Cadence, or Siemens.
• Strong debugging and problem-solving skills.

Responsibilities

• Define RTL micro-architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, adaptive equalization, CDR loops).
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues; support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues, and support PHY integration and system-level debugging.

Skills

SystemVerilog

RTL development

DSP hardware

Synchronous design

Education

Electrical/ECE degree

Tools

Synopsys

Cadence

Siemens

Job description

Credo is seeking a Senior Staff PHY RTL Design Engineer at its San Jose, CA headquarters to lead RTL architecture, design, implementation and verification of SerDes DSP blocks for high-performance networking and data center products.

The ideal candidate has strong RTL development experience with SystemVerilog and a solid background in high-speed SerDes architectures, ASIC flows, and debugging. Onsite role with comprehensive compensation and bonus eligibility.