Senior Staff GPU Verification Engineer – Subsystems

Samsung Electronics America

San Jose (CA)

On-site

USD 180,000 - 297,000

Full time

14 days+
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Job summary

Samsung Electronics America is seeking a Senior Staff GPU Design Verification Engineer – Subsystems to lead verification for next‑gen mobile GPU subsystems. You will architect verification plans, define goals, and drive coverage and sign‑offs across blocks and interfaces, collaborating with architecture and software teams.

You will design scalable verification environments using SystemVerilog, UVM, and C++, applying constrained‑random testing and assertion techniques to ensure functional

Qualifications

  • 8+ years hands-on experience in GPU, CPU, or advanced semiconductor design verification.
  • Strong understanding of computer architecture and GPU subsystem design, including block- and subsystem-level integration.
  • Proficient in SystemVerilog, UVM, constrained-random testing, functional coverage, and assertions.
  • Experience building configurable UVM testbenches for reuse across hierarchies.

Responsibilities

  • Define verification strategy and goals for GPU subsystems.
  • Develop verification environments and scalable test scenarios across blocks and interfaces.
  • Conduct debugging, root-cause analysis, and issue resolution with design/architecture teams.
  • Mentor engineers and advance verification methodologies and tooling.

Skills

GPU verification
UVM
SystemVerilog
C/C++
Python

Education

Bachelor's degree in CS/Engineering
Master's degree in related field

Tools

UVM
SystemVerilog
C++
Python

Job description

Samsung Electronics America is seeking a Senior Staff GPU Design Verification Engineer – Subsystems to lead verification for next‑gen mobile GPU subsystems. You will architect verification plans, define goals, and drive coverage and sign‑offs across blocks and interfaces, collaborating with architecture and software teams.

You will design scalable verification environments using SystemVerilog, UVM, and C++, applying constrained‑random testing and assertion techniques to ensure functional

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