Senior Staff Digital Design Engineer: SoC Architect

SmartRecruiters, Inc.; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Renesas Electronics is seeking a Sr Staff Digital Design Engineer to lead digital architecture, RTL development, and SoC integration for advanced mixed‑signal ICs. You will work across architecture, verification, DFT, physical design, firmware, and analog teams from concept through silicon validation and production release.

The ideal candidate has strong RTL/SoC experience, multi‑clock design expertise, and a track record of silicon sign‑off.

Qualifications

• MSEE or Ph.D. in Electrical Engineering with 8+ years of relevant industry experience, or BSEE with 12+ years.
• Strong background in digital IC and SoC architecture, design, and implementation.
• Experience with SoC interconnects and protocols including AHB, APB, AXI, USB, I2C/I3C, SPI, and UART.
• Strong knowledge of embedded memory architectures including SRAM, OTP, MTP, and Flash.
• Extensive hands‑on experience with RTL design using Verilog/SystemVerilog.
• Experience with the complete ASIC/SoC development flow, including RTL design, SoC integration, lint checks, CDC/RDC verification, synthesis, DFT, STA, timing closure, and signoff.
• Strong understanding of multi‑clock designs, reset architecture, and low‑power design methodologies.
• Experience driving technical debug and resolution of functional, timing, and silicon issues.

Responsibilities

• Define digital architecture and micro‑architecture for complex mixed‑signal and SoC products.
• Develop high‑quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.
• Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
• Work with physical design teams to achieve power, performance, and area goals.
• Perform silicon bring‑up, debug, characterization, and root‑cause analysis of silicon issues.
• Create and maintain design documentation throughout the development cycle.
• Contribute to technology and architecture definition for future product generations.

Skills

Digital IC Architecture

RTL Design

SoC Integration

STA/Timing Closure

DFT/Testing

SoC interconnects (AHB/APB/AXI)

Embedded memory architectures

Verilog/SystemVerilog

Education

MSEE or Ph.D. in Electrical Engineering

BSEE with 12+ years

Tools

Synopsys Design Compiler

PrimeTime

SpyGlass

Cadence

VC Static

Verdi

Job description

Renesas Electronics is seeking a Sr Staff Digital Design Engineer to lead digital architecture, RTL development, and SoC integration for advanced mixed‑signal ICs. You will work across architecture, verification, DFT, physical design, firmware, and analog teams from concept through silicon validation and production release.

The ideal candidate has strong RTL/SoC experience, multi‑clock design expertise, and a track record of silicon sign‑off.