Senior Staff SoC Digital Design Architect

Renesaselectronics; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Renesas is seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group in San Jose, CA. You will lead architecture, RTL development, and SoC integration across mixed-signal ICs, working with cross-functional teams from architecture to production.

The role requires strong RTL skills, Verilog/SystemVerilog, and a track record delivering silicon, with responsibilities spanning timing, DFT, test methodologies, and design signoff.

Qualifications

• Experience in digital IC and SoC architecture, design, and implementation.

Responsibilities

• Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.
• Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
• Work with physical design teams to achieve power, performance, and area goals.
• Perform silicon bring-up, debug, characterization, and root-cause analysis of silicon issues.
• Create and maintain design documentation throughout the development cycle.
• Contribute to technology and architecture definition for future product generations.

Skills

RTL design

Verilog/SystemVerilog

SoC integration

Timing closure

DFT

Debugging

Education

MSEE or Ph.D. in Electrical Engineering

BSEE

Tools

Synopsys Design Compiler

PrimeTime

SpyGlass

Verdi

Cadence design environments

Job description

Renesas is seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group in San Jose, CA. You will lead architecture, RTL development, and SoC integration across mixed-signal ICs, working with cross-functional teams from architecture to production.

The role requires strong RTL skills, Verilog/SystemVerilog, and a track record delivering silicon, with responsibilities spanning timing, DFT, test methodologies, and design signoff.