Sr Staff Digital Engineer

Renesaselectronics; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Renesas is seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group in San Jose, CA. You will lead architecture, RTL development, and SoC integration across mixed-signal ICs, working with cross-functional teams from architecture to production.

The role requires strong RTL skills, Verilog/SystemVerilog, and a track record delivering silicon, with responsibilities spanning timing, DFT, test methodologies, and design signoff.

Qualifications

• Experience in digital IC and SoC architecture, design, and implementation.

Responsibilities

• Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.
• Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
• Work with physical design teams to achieve power, performance, and area goals.
• Perform silicon bring-up, debug, characterization, and root-cause analysis of silicon issues.
• Create and maintain design documentation throughout the development cycle.
• Contribute to technology and architecture definition for future product generations.

Skills

RTL design

Verilog/SystemVerilog

SoC integration

Timing closure

DFT

Debugging

Education

MSEE or Ph.D. in Electrical Engineering

BSEE

Tools

Synopsys Design Compiler

PrimeTime

SpyGlass

Verdi

Cadence design environments

Job description

Renesas is a global semiconductor company providing hardware and software solutions for various cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, a publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multicultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data centers and strengthening our presence in the industrial/IoT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics.

At Renesas, you will be part of a global engineering organization that values technical excellence, innovation, and collaboration. We offer opportunities to work on complex mixed-signal and digital SoC products with teams distributed across the United States and Asia, contributing to cutting‑edge semiconductor solutions from concept to production.

We are seeking an experienced Sr Staff Digital Design Engineer to join the Analog & Connectivity Business Group. In this role, you will be responsible for the architecture, design, integration, and implementation of advanced digital and mixed‑signal ICs and SoCs. The ideal candidate possesses strong expertise in digital design methodologies, RTL development, SoC integration, and design signoff, with a proven track record of delivering successful silicon products.

You will work closely with architecture, verification, DFT, physical design, firmware, and analog design teams throughout the product development lifecycle, from specification and architecture definition through silicon validation and production release.

Responsibilities

• Define digital architecture and micro-architecture for complex mixed-signal and SoC products.
• Develop high-quality RTL using Verilog/SystemVerilog and participate in design reviews.
• Drive SoC and subsystem integration, including internal bus architectures and peripheral interfaces.
• Develop and validate timing constraints, synthesis scripts, and implementation flows.
• Analyze and resolve CDC, RDC, Lint, and timing issues to achieve design signoff.
• Collaborate with verification teams on test planning, coverage closure, and debugging.
• Support DFT implementation including scan, MBIST, JTAG, and production test methodologies.
• Work with physical design teams to achieve power, performance, and area goals.
• Perform silicon bring-up, debug, characterization, and root-cause analysis of silicon issues.
• Create and maintain design documentation throughout the development cycle.
• Contribute to technology and architecture definition for future product generations.

• MSEE or Ph.D. in Electrical Engineering with 8+ years of relevant industry experience, or BSEE with 12+ years of relevant industry experience.
• Strong background in digital IC and SoC architecture, design, and implementation.
• Proven experience with SoC interconnects and protocols including AHB, APB, AXI, USB, I2C/I3C, SPI, and UART.
• Strong knowledge of embedded memory architectures including SRAM, OTP, MTP, and Flash.
• Extensive hands‑on experience with RTL design using Verilog/SystemVerilog.
• Experience with the complete ASIC/SoC development flow, including:
• RTL design and simulation
• SoC integration
• Lint and design quality checks
• CDC and RDC verification
• Logic synthesis
• DFT implementation
• SDC constraint development
• Static Timing Analysis (STA)
• Timing closure and design signoff
• Strong understanding of multi-clock designs, reset architecture, and low-power design methodologies.
• Experience driving technical debug and resolution of functional, timing, and silicon issues.
• Strong communication, problem-solving, and teamwork skills.
• Highly motivated self-starter with a passion for technical innovation.
• AI savvy and able to leverage AI tools to improve engineering productivity and design quality.

Preferred

• Mixed‑signal IC development experience and understanding of analog/digital integration challenges.
• Experience with industry-standard EDA tools such as Synopsys Design Compiler, PrimeTime, SpyGlass, VC Static, Verdi, and Cadence design environments.
• Hands‑on experience integrating and debugging Arm® processor subsystems (Cortex‑M0, Cortex‑M0+, Cortex‑M3, Cortex‑M33, or similar Arm cores), including AHB/APB interconnects, memory subsystems, interrupt controllers, debug infrastructure, boot flows, and firmware interaction.
• Experience with high‑speed interface design and implementation.
• Familiarity with FPGA prototyping and emulation flows.
• Mandarin language proficiency is a plus due to collaboration with engineering teams i