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Benefits offered by this job
Comprehensive Health Care Plan
Retirement Savings Matching Program
Generous Time Off
Paid Family Leave
Flexible, hybrid workplace model
Equity grants
Job summary
A leading AI infrastructure firm in Boston seeks a Mid-Senior Level Design Verification Engineer. This role emphasizes defining DV methodologies and collaborating across engineering teams. Candidates should have 8+ years of design verification experience and proficiency in SystemVerilog and Python. The position offers a competitive salary range of $206,000 - $236,000 along with comprehensive benefits including health care and equity grants. Join a pioneering team dedicated to revolutionizing AI technology.
Qualifications
Minimum of 8 years of design verification experience.
2+ years of experience in Python programming.
Expertise with UVM library for test planning.
Responsibilities
Define DV methodologies for integrated devices.
Create and execute test plans for high-quality tapeouts.
Collaborate with engineers to define validation flows.
Develop reusable test bench components for verification.
Skills
Design verification
SystemVerilog
Python
UVM library
Xcelium
ModelSim
Questa
VCS
Problem solving
Collaboration
Education
Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering
Tools
Emulation tools
Job description
A leading AI infrastructure firm in Boston seeks a Mid-Senior Level Design Verification Engineer. This role emphasizes defining DV methodologies and collaborating across engineering teams. Candidates should have 8+ years of design verification experience and proficiency in SystemVerilog and Python. The position offers a competitive salary range of $206,000 - $236,000 along with comprehensive benefits including health care and equity grants. Join a pioneering team dedicated to revolutionizing AI technology.