Senior Space-Grade FPGA & ASIC Design Engineer

ApTask; California; On-site; USD 150,000 - 230,000; Full time

Job summary

ApTask is assisting a leading aerospace client in California to fill a Senior ASIC/FPGA Design role. The team focuses on reusable rocket technology and high-assurance digital ICs used in spaceflight systems.

The candidate will design and verify digital ASICs and FPGAs, develop test benches, perform timing and signoff, and work with cross-functional groups across systems and firmware teams. Strong HDL expertise and a track record in full lifecycle IC projects are required.

Qualifications

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Experience with FPGA & ASIC design and HDL programming (VHDL/Verilog/SystemVerilog).

Responsibilities

• Design and develop digital ASICs and FPGAs, and/or mixed-signal ASICs with HDL (VHDL, Verilog, SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing analysis, noise analysis, and other signoff checks.
• Collaborate with cross-functional teams including systems, firmware, architecture, and product engineering.
• Support lab integration and troubleshooting activities.
• Resolve design issues and drive solutions for timing, congestion, and other implementation challenges.

Skills

ASIC design

HDL programming

FPGA design

Verification

Timing analysis

Cross-functional collaboration

Python scripting

Education

Bachelors in Electrical/Computer Engineering

Tools

EDA tools

RTL2GDSII

Job description

ApTask is assisting a leading aerospace client in California to fill a Senior ASIC/FPGA Design role. The team focuses on reusable rocket technology and high-assurance digital ICs used in spaceflight systems.

The candidate will design and verify digital ASICs and FPGAs, develop test benches, perform timing and signoff, and work with cross-functional groups across systems and firmware teams. Strong HDL expertise and a track record in full lifecycle IC projects are required.